{"id":2222943,"url":"http://patchwork.ozlabs.org/api/patches/2222943/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260414053715.1378021-7-gaurav.sharma_7@nxp.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260414053715.1378021-7-gaurav.sharma_7@nxp.com>","list_archive_url":null,"date":"2026-04-14T05:37:06","name":"[PATCHv5,06/15] hw/arm/fsl-imx8mm: Adding support for USDHC storage controllers","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"04701abd45a55a473b7e041f972cae75d329fb94","submitter":{"id":92057,"url":"http://patchwork.ozlabs.org/api/people/92057/?format=json","name":"Gaurav Sharma","email":"gaurav.sharma_7@nxp.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260414053715.1378021-7-gaurav.sharma_7@nxp.com/mbox/","series":[{"id":499777,"url":"http://patchwork.ozlabs.org/api/series/499777/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499777","date":"2026-04-14T05:37:06","name":"Adding comprehensive support for i.MX8MM EVK board","version":1,"mbox":"http://patchwork.ozlabs.org/series/499777/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222943/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222943/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":"legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)","Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fvtNL1Xv4z1y2d\n\tfor ; Tue, 14 Apr 2026 15:38:08 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wCWSm-0003oe-Kx; Tue, 14 Apr 2026 01:37:28 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wCWSj-0003nX-NM\n for qemu-devel@nongnu.org; Tue, 14 Apr 2026 01:37:27 -0400","from inva021.nxp.com ([92.121.34.21])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wCWSg-00044M-Rl\n for qemu-devel@nongnu.org; Tue, 14 Apr 2026 01:37:25 -0400","from inva021.nxp.com (localhost [127.0.0.1])\n by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id BB40E202240;\n Tue, 14 Apr 2026 07:37:21 +0200 (CEST)","from aprdc01srsp001v.ap-rdc01.nxp.com\n (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16])\n by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 865A1202239;\n Tue, 14 Apr 2026 07:37:21 +0200 (CEST)","from lsv031015.swis.in-blr01.nxp.com\n (lsv031015.swis.in-blr01.nxp.com [10.12.177.77])\n by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 02EB018000A4;\n Tue, 14 Apr 2026 13:37:20 +0800 (+08)"],"From":"Gaurav Sharma ","To":"qemu-devel@nongnu.org","Cc":"pbonzini@redhat.com, peter.maydell@linaro.org,\n Gaurav Sharma ,\n Philippe Mathieu-Daude ","Subject":"[PATCHv5 06/15] hw/arm/fsl-imx8mm: Adding support for USDHC storage\n controllers","Date":"Tue, 14 Apr 2026 11:07:06 +0530","Message-Id":"<20260414053715.1378021-7-gaurav.sharma_7@nxp.com>","X-Mailer":"git-send-email 2.34.1","In-Reply-To":"<20260414053715.1378021-1-gaurav.sharma_7@nxp.com>","References":"<20260414053715.1378021-1-gaurav.sharma_7@nxp.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Virus-Scanned":"ClamAV using ClamSMTP","Received-SPF":"pass client-ip=92.121.34.21;\n envelope-from=gaurav.sharma_7@nxp.com; helo=inva021.nxp.com","X-Spam_score_int":"-41","X-Spam_score":"-4.2","X-Spam_bar":"----","X-Spam_report":"(-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"It enables emulation of SD/MMC cards through a virtual SDHCI interface\nThe emulated SDHCI controller allows guest OS to use emulated storage as\na standard block device.\nThis will allow running the images such as those generated\nby Buildroot.\n\nReviewed-by: Philippe Mathieu-Daude \nReviewed-by: Peter Maydell \nSigned-off-by: Gaurav Sharma \n---\n hw/arm/Kconfig | 1 +\n hw/arm/fsl-imx8mm.c | 25 +++++++++++++++++++++++++\n hw/arm/imx8mm-evk.c | 17 +++++++++++++++++\n include/hw/arm/fsl-imx8mm.h | 7 +++++++\n 4 files changed, 50 insertions(+)","diff":"diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig\nindex c785f3f3a3..ba37ab2808 100644\n--- a/hw/arm/Kconfig\n+++ b/hw/arm/Kconfig\n@@ -624,6 +624,7 @@ config FSL_IMX8MM\n select FSL_IMX8MP_ANALOG\n select FSL_IMX8MP_CCM\n select IMX\n+ select SDHCI\n \n config FSL_IMX8MM_EVK\n bool\ndiff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c\nindex 8999bc701e..2a4d4d5e6d 100644\n--- a/hw/arm/fsl-imx8mm.c\n+++ b/hw/arm/fsl-imx8mm.c\n@@ -180,6 +180,10 @@ static void fsl_imx8mm_init(Object *obj)\n object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);\n }\n \n+ for (i = 0; i < FSL_IMX8MM_NUM_USDHCS; i++) {\n+ g_autofree char *name = g_strdup_printf(\"usdhc%d\", i + 1);\n+ object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);\n+ }\n }\n \n static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n@@ -357,6 +361,26 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n fsl_imx8mm_memmap[FSL_IMX8MM_OCRAM].addr,\n &s->ocram);\n \n+ /* USDHCs */\n+ for (i = 0; i < FSL_IMX8MM_NUM_USDHCS; i++) {\n+ static const struct {\n+ hwaddr addr;\n+ unsigned int irq;\n+ } usdhc_table[FSL_IMX8MM_NUM_USDHCS] = {\n+ { fsl_imx8mm_memmap[FSL_IMX8MM_USDHC1].addr, FSL_IMX8MM_USDHC1_IRQ },\n+ { fsl_imx8mm_memmap[FSL_IMX8MM_USDHC2].addr, FSL_IMX8MM_USDHC2_IRQ },\n+ { fsl_imx8mm_memmap[FSL_IMX8MM_USDHC3].addr, FSL_IMX8MM_USDHC3_IRQ },\n+ };\n+\n+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), errp)) {\n+ return;\n+ }\n+\n+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0, usdhc_table[i].addr);\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0,\n+ qdev_get_gpio_in(gicdev, usdhc_table[i].irq));\n+ }\n+\n /* SNVS */\n if (!sysbus_realize(SYS_BUS_DEVICE(&s->snvs), errp)) {\n return;\n@@ -375,6 +399,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n case FSL_IMX8MM_OCRAM:\n case FSL_IMX8MM_SNVS_HP:\n case FSL_IMX8MM_UART1 ... FSL_IMX8MM_UART4:\n+ case FSL_IMX8MM_USDHC1 ... FSL_IMX8MM_USDHC3:\n /* device implemented and treated above */\n break;\n \ndiff --git a/hw/arm/imx8mm-evk.c b/hw/arm/imx8mm-evk.c\nindex 0a8cce8866..dfdf3cd4f8 100644\n--- a/hw/arm/imx8mm-evk.c\n+++ b/hw/arm/imx8mm-evk.c\n@@ -84,6 +84,23 @@ static void imx8mm_evk_init(MachineState *machine)\n memory_region_add_subregion(get_system_memory(), FSL_IMX8MM_RAM_START,\n machine->ram);\n \n+ for (int i = 0; i < FSL_IMX8MM_NUM_USDHCS; i++) {\n+ BusState *bus;\n+ DeviceState *carddev;\n+ BlockBackend *blk;\n+ DriveInfo *di = drive_get(IF_SD, i, 0);\n+\n+ if (!di) {\n+ continue;\n+ }\n+\n+ blk = blk_by_legacy_dinfo(di);\n+ bus = qdev_get_child_bus(DEVICE(&s->usdhc[i]), \"sd-bus\");\n+ carddev = qdev_new(TYPE_SD_CARD);\n+ qdev_prop_set_drive_err(carddev, \"drive\", blk, &error_fatal);\n+ qdev_realize_and_unref(carddev, bus, &error_fatal);\n+ }\n+\n if (!qtest_enabled()) {\n arm_load_kernel(&s->cpu[0], machine, &boot_info);\n }\ndiff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h\nindex 8a172b89e0..93a30a2f55 100644\n--- a/include/hw/arm/fsl-imx8mm.h\n+++ b/include/hw/arm/fsl-imx8mm.h\n@@ -16,6 +16,7 @@\n #include \"hw/misc/imx7_snvs.h\"\n #include \"hw/misc/imx8mp_analog.h\"\n #include \"hw/misc/imx8mp_ccm.h\"\n+#include \"hw/sd/sdhci.h\"\n #include \"qom/object.h\"\n #include \"qemu/units.h\"\n \n@@ -29,6 +30,7 @@ enum FslImx8mmConfiguration {\n FSL_IMX8MM_NUM_CPUS = 4,\n FSL_IMX8MM_NUM_IRQS = 128,\n FSL_IMX8MM_NUM_UARTS = 4,\n+ FSL_IMX8MM_NUM_USDHCS = 3,\n };\n \n struct FslImx8mmState {\n@@ -41,6 +43,7 @@ struct FslImx8mmState {\n IMX7SNVSState snvs;\n IMXSerialState uart[FSL_IMX8MM_NUM_UARTS];\n MemoryRegion ocram;\n+ SDHCIState usdhc[FSL_IMX8MM_NUM_USDHCS];\n };\n \n enum FslImx8mmMemoryRegions {\n@@ -155,6 +158,10 @@ enum FslImx8mmMemoryRegions {\n };\n \n enum FslImx8mmIrqs {\n+ FSL_IMX8MM_USDHC1_IRQ = 22,\n+ FSL_IMX8MM_USDHC2_IRQ = 23,\n+ FSL_IMX8MM_USDHC3_IRQ = 24,\n+\n FSL_IMX8MM_UART1_IRQ = 26,\n FSL_IMX8MM_UART2_IRQ = 27,\n FSL_IMX8MM_UART3_IRQ = 28,\n","prefixes":["PATCHv5","06/15"]}