{"id":2222721,"url":"http://patchwork.ozlabs.org/api/patches/2222721/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260413-waveshare-dsi-touch-v3-10-3aeb53022c32@oss.qualcomm.com/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260413-waveshare-dsi-touch-v3-10-3aeb53022c32@oss.qualcomm.com>","list_archive_url":null,"date":"2026-04-13T14:05:33","name":"[v3,10/21] drm/panel: himax-hx8394: support Waveshare DSI panels","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"61802618ca0b7fd55513a930ffa354bd96893419","submitter":{"id":90483,"url":"http://patchwork.ozlabs.org/api/people/90483/?format=json","name":"Dmitry Baryshkov","email":"dmitry.baryshkov@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260413-waveshare-dsi-touch-v3-10-3aeb53022c32@oss.qualcomm.com/mbox/","series":[{"id":499710,"url":"http://patchwork.ozlabs.org/api/series/499710/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=499710","date":"2026-04-13T14:05:24","name":"drm/panel: support Waveshare DSI TOUCH kits","version":3,"mbox":"http://patchwork.ozlabs.org/series/499710/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222721/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222721/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com 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Ondrej Jirman ,\n Javier Martinez Canillas ,\n Jagan Teki , Liam Girdwood ,\n Mark Brown , Linus Walleij ,\n Bartosz Golaszewski ,\n Jie Gan ","Cc":"dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,\n linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org","X-Mailer":"b4 0.15.1","X-Developer-Signature":"v=1; a=openpgp-sha256; l=11490;\n i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id;\n bh=I07ADQdGhA6Qq6Cx74/dBgFSnA/ZPawbvmK6jOC9m5A=;\n b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBp3Pgn0ktOsN3lYk3onhc6d2vt/kaLqOOW/m/f9\n 4bNVrZ62ryJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCadz4JwAKCRCLPIo+Aiko\n 1VjQCACgk8k2Tw1AzVZ0mNgCaAm2wd6gCiO8zFYtlH6PKjClW0NM9IMyYzg6ROc1/20FhMCPIek\n FKa3Opo28Jn1PucjAroDZXpVN2aNCl7MsCsKEH82pch9TjOjmmYHKf56NXnmexZwD4RRdGIoLOH\n /jFWX9FQmydrmL/X/ZAeuDCI4YdiupVc9imgiaNZfkAWWxkEZdsJ9IaLJ7pe1oHjPE6qpwQme5S\n XLQg7LoY6TMSOL3SXgKZM0XGzcGBhDgyC/nAdDf3SsrEgHvHamRHZOIlTNNWwFdl2abX9OmeW+I\n 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\n---\n drivers/gpu/drm/panel/panel-himax-hx8394.c | 244 +++++++++++++++++++++++++++++\n 1 file changed, 244 insertions(+)","diff":"diff --git a/drivers/gpu/drm/panel/panel-himax-hx8394.c b/drivers/gpu/drm/panel/panel-himax-hx8394.c\nindex 1f23c50b6661..bf80354567df 100644\n--- a/drivers/gpu/drm/panel/panel-himax-hx8394.c\n+++ b/drivers/gpu/drm/panel/panel-himax-hx8394.c\n@@ -44,6 +44,7 @@\n #define HX8394_CMD_SETID\t 0xc3\n #define HX8394_CMD_SETDDB\t 0xc4\n #define HX8394_CMD_UNKNOWN2\t 0xc6\n+#define HX8394_CMD_UNKNOWN6\t 0xc7\n #define HX8394_CMD_SETCABC\t 0xc9\n #define HX8394_CMD_SETCABCGAIN\t 0xca\n #define HX8394_CMD_SETPANEL\t 0xcc\n@@ -618,6 +619,247 @@ static const struct hx8394_panel_desc hl055fhav028c_desc = {\n \t.init_sequence = hl055fhav028c_init_sequence,\n };\n \n+static void waveshare_5_0_inch_a_init_sequence(struct mipi_dsi_multi_context *dsi_ctx)\n+{\n+\t/* 5.19.8 SETEXTC: Set extension command (B9h) */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETEXTC,\n+\t\t\t\t 0xff, 0x83, 0x94);\n+\n+\t/* 5.19.2 SETPOWER: Set power (B1h) */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPOWER,\n+\t\t\t\t 0x48, 0x0a, 0x6a, 0x09, 0x33, 0x54, 0x71, 0x71, 0x2e, 0x45);\n+\n+\t/* 5.19.9 SETMIPI: Set MIPI control (BAh) */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETMIPI,\n+\t\t\t\t 0x61, 0x03, 0x68, 0x6b, 0xb2, 0xc0);\n+\n+\t/* 5.19.3 SETDISP: Set display related register (B2h) */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETDISP,\n+\t\t\t\t 0x00, 0x80, 0x64, 0x0c, 0x06, 0x2f);\n+\n+\t/* 5.19.4 SETCYC: Set display waveform cycles (B4h) */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETCYC,\n+\t\t\t\t 0x1c, 0x78, 0x1c, 0x78, 0x1c, 0x78, 0x01, 0x0c, 0x86, 0x75,\n+\t\t\t\t 0x00, 0x3f, 0x1c, 0x78, 0x1c, 0x78, 0x1c, 0x78, 0x01, 0x0c,\n+\t\t\t\t 0x86);\n+\n+\t/* 5.19.19 SETGIP0: Set GIP Option0 (D3h) */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP0,\n+\t\t\t\t 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x32, 0x10,\n+\t\t\t\t 0x05, 0x00, 0x05, 0x32, 0x13, 0xc1, 0x00, 0x01, 0x32, 0x10,\n+\t\t\t\t 0x08, 0x00, 0x00, 0x37, 0x03, 0x07, 0x07, 0x37, 0x05, 0x05,\n+\t\t\t\t 0x37, 0x0c, 0x40);\n+\n+\t/* 5.19.20 Set GIP Option1 (D5h) */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP1,\n+\t\t\t\t 0x18, 0x18, 0x18, 0x18, 0x22, 0x23, 0x20, 0x21, 0x04, 0x05,\n+\t\t\t\t 0x06, 0x07, 0x00, 0x01, 0x02, 0x03, 0x18, 0x18, 0x18, 0x18,\n+\t\t\t\t 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n+\t\t\t\t 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n+\t\t\t\t 0x19, 0x19, 0x19, 0x19);\n+\n+\t/* 5.19.21 Set GIP Option2 (D6h) */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP2,\n+\t\t\t\t 0x18, 0x18, 0x19, 0x19, 0x21, 0x20, 0x23, 0x22, 0x03, 0x02,\n+\t\t\t\t 0x01, 0x00, 0x07, 0x06, 0x05, 0x04, 0x18, 0x18, 0x18, 0x18,\n+\t\t\t\t 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n+\t\t\t\t 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n+\t\t\t\t 0x19, 0x19, 0x18, 0x18);\n+\n+\t/* 5.19.25 SETGAMMA: Set gamma curve related setting (E0h) */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGAMMA,\n+\t\t\t\t 0x07, 0x08, 0x09, 0x0d, 0x10, 0x14, 0x16, 0x13, 0x24, 0x36,\n+\t\t\t\t 0x48, 0x4a, 0x58, 0x6f, 0x76, 0x80, 0x97, 0xa5, 0xa8, 0xb5,\n+\t\t\t\t 0xc6, 0x62, 0x63, 0x68, 0x6f, 0x72, 0x78, 0x7f, 0x7f, 0x00,\n+\t\t\t\t 0x02, 0x08, 0x0d, 0x0c, 0x0e, 0x0f, 0x10, 0x24, 0x36, 0x48,\n+\t\t\t\t 0x4a, 0x58, 0x6f, 0x78, 0x82, 0x99, 0xa4, 0xa0, 0xb1, 0xc0,\n+\t\t\t\t 0x5e, 0x5e, 0x64, 0x6b, 0x6c, 0x73, 0x7f, 0x7f);\n+\n+\t/* 5.19.17 SETPANEL (CCh) */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPANEL,\n+\t\t\t\t 0x0b);\n+\n+\t/* Unknown command, not listed in the HX8394-F datasheet */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN1,\n+\t\t\t\t 0x1f, 0x73);\n+\n+\t/* 5.19.5 SETVCOM: Set VCOM voltage (B6h) */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETVCOM,\n+\t\t\t\t 0x6b, 0x6b);\n+\n+\t/* Unknown command, not listed in the HX8394-F datasheet */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN3,\n+\t\t\t\t 0x02);\n+\n+\t/* 5.19.11 Set register bank (BDh) */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK,\n+\t\t\t\t 0x01);\n+\n+\t/* 5.19.2 SETPOWER: Set power (B1h) */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPOWER,\n+\t\t\t\t 0x00);\n+\n+\t/* 5.19.11 Set register bank (BDh) */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK,\n+\t\t\t\t 0x00);\n+\n+\t/* Unknown command, not listed in the HX8394-F datasheet */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN5,\n+\t\t\t\t 0x40, 0x81, 0x50, 0x00, 0x1a, 0xfc, 0x01);\n+};\n+\n+static const struct drm_display_mode waveshare_5_0_inch_a_mode = {\n+\t.clock = 70000,\n+\t.hdisplay = 720,\n+\t.hsync_start = 720 + 40,\n+\t.hsync_end = 720 + 40 + 20,\n+\t.htotal = 720 + 40 + 20 + 20,\n+\t.vdisplay = 1280,\n+\t.vsync_start = 1280 + 30,\n+\t.vsync_end = 1280 + 30 + 10,\n+\t.vtotal = 1280 + 30 + 10 + 4,\n+\t.width_mm = 62,\n+\t.height_mm = 110,\n+};\n+\n+static const struct hx8394_panel_desc waveshare_5_0_inch_a_desc = {\n+\t.mode = &waveshare_5_0_inch_a_mode,\n+\t.lanes = 2,\n+\t.mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |\n+\t\t MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,\n+\t.format = MIPI_DSI_FMT_RGB888,\n+\t.init_sequence = waveshare_5_0_inch_a_init_sequence,\n+};\n+\n+static const struct drm_display_mode waveshare_5_5_inch_a_mode = {\n+\t.clock = 65000,\n+\t.hdisplay = 720,\n+\t.hsync_start = 720 + 50,\n+\t.hsync_end = 720 + 50 + 50,\n+\t.htotal = 720 + 50 + 50 + 10,\n+\t.vdisplay = 1280,\n+\t.vsync_start = 1280 + 15,\n+\t.vsync_end = 1280 + 15 + 12,\n+\t.vtotal = 1280 + 15 + 12 + 4,\n+\t.width_mm = 62,\n+\t.height_mm = 110,\n+};\n+\n+static void waveshare_5_5_inch_a_init_sequence(struct mipi_dsi_multi_context *dsi_ctx)\n+{\n+\t/* 5.19.8 SETEXTC: Set extension command (B9h) */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETEXTC,\n+\t\t\t\t 0xff, 0x83, 0x94);\n+\n+\t/* 5.19.9 SETMIPI: Set MIPI control (BAh) */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETMIPI,\n+\t\t\t\t 0x61, 0x03, 0x68, 0x6b, 0xb2, 0xc0);\n+\n+\t/* 5.19.2 SETPOWER: Set power (B1h) */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPOWER,\n+\t\t\t\t 0x48, 0x12, 0x72, 0x09, 0x32, 0x54, 0x71, 0x71, 0x57, 0x47);\n+\n+\t/* 5.19.3 SETDISP: Set display related register (B2h) */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETDISP,\n+\t\t\t\t 0x00, 0x80, 0x64, 0x0c, 0x0d, 0x2f);\n+\n+\t/* 5.19.4 SETCYC: Set display waveform cycles (B4h) */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETCYC,\n+\t\t\t\t 0x73, 0x74, 0x73, 0x74, 0x73, 0x74, 0x01, 0x0c, 0x86, 0x75,\n+\t\t\t\t 0x00, 0x3f, 0x73, 0x74, 0x73, 0x74, 0x73, 0x74, 0x01, 0x0c,\n+\t\t\t\t 0x86);\n+\n+\t/* 5.19.5 SETVCOM: Set VCOM voltage (B6h) */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETVCOM,\n+\t\t\t\t 0x86, 0x86);\n+\n+\t/* 5.19.19 SETGIP0: Set GIP Option0 (D3h) */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP0,\n+\t\t\t\t 0x00, 0x00, 0x07, 0x07, 0x40, 0x07, 0x0c, 0x00, 0x08, 0x10,\n+\t\t\t\t 0x08, 0x00, 0x08, 0x54, 0x15, 0x0a, 0x05, 0x0a, 0x02, 0x15,\n+\t\t\t\t 0x06, 0x05, 0x06, 0x47, 0x44, 0x0a, 0x0a, 0x4b, 0x10, 0x07,\n+\t\t\t\t 0x07, 0x0c, 0x40);\n+\n+\t/* 5.19.20 Set GIP Option1 (D5h) */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP1,\n+\t\t\t\t 0x1c, 0x1c, 0x1d, 0x1d, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,\n+\t\t\t\t 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x24, 0x25, 0x18, 0x18,\n+\t\t\t\t 0x26, 0x27, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n+\t\t\t\t 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x20, 0x21,\n+\t\t\t\t 0x18, 0x18, 0x18, 0x18);\n+\n+\t/* 5.19.21 Set GIP Option2 (D6h) */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP2,\n+\t\t\t\t 0x1c, 0x1c, 0x1d, 0x1d, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02,\n+\t\t\t\t 0x01, 0x00, 0x0b, 0x0a, 0x09, 0x08, 0x21, 0x20, 0x18, 0x18,\n+\t\t\t\t 0x27, 0x26, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n+\t\t\t\t 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x25, 0x24,\n+\t\t\t\t 0x18, 0x18, 0x18, 0x18);\n+\n+\t/* 5.19.25 SETGAMMA: Set gamma curve related setting (E0h) */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGAMMA,\n+\t\t\t\t 0x00, 0x13, 0x21, 0x28, 0x2b, 0x2e, 0x32, 0x2f, 0x61, 0x6e,\n+\t\t\t\t 0x7e, 0x7b, 0x80, 0x8f, 0x91, 0x93, 0x9d, 0x9d, 0x97, 0xa4,\n+\t\t\t\t 0xb1, 0x57, 0x55, 0x58, 0x5d, 0x60, 0x67, 0x74, 0x7f, 0x00,\n+\t\t\t\t 0x13, 0x21, 0x28, 0x2b, 0x2e, 0x32, 0x2f, 0x61, 0x6e, 0x7d,\n+\t\t\t\t 0x7b, 0x7f, 0x8e, 0x90, 0x93, 0x9c, 0x9d, 0x98, 0xa4, 0xb1,\n+\t\t\t\t 0x58, 0x55, 0x59, 0x5e, 0x61, 0x68, 0x76, 0x7f);\n+\n+\t/* Unknown command, not listed in the HX8394-F datasheet */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN1,\n+\t\t\t\t 0x1f, 0x31);\n+\n+\t/* 5.19.17 SETPANEL (CCh) */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPANEL,\n+\t\t\t\t 0x07);\n+\n+\t/* Unknown command, not listed in the HX8394-F datasheet */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN3,\n+\t\t\t\t 0x02);\n+\n+\t/* 5.19.11 Set register bank (BDh) */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK,\n+\t\t\t\t 0x02);\n+\n+\t/* Unknown command, not listed in the HX8394-F datasheet */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN4,\n+\t\t\t\t 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n+\t\t\t\t 0xff, 0xff);\n+\n+\t/* 5.19.11 Set register bank (BDh) */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK,\n+\t\t\t\t 0x00);\n+\n+\t/* 5.19.11 Set register bank (BDh) */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK,\n+\t\t\t\t 0x01);\n+\n+\t/* 5.19.2 SETPOWER: Set power (B1h) */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPOWER,\n+\t\t\t\t 0x00);\n+\n+\t/* 5.19.11 Set register bank (BDh) */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK,\n+\t\t\t\t 0x00);\n+\n+\t/* Unknown command, not listed in the HX8394-F datasheet */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN2,\n+\t\t\t\t 0xed);\n+\n+\t/* Unknown command, not listed in the HX8394-F datasheet */\n+\tmipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN6,\n+\t\t\t\t 0x00, 0xc0);\n+};\n+\n+static const struct hx8394_panel_desc waveshare_5_5_inch_a_desc = {\n+\t.mode = &waveshare_5_5_inch_a_mode,\n+\t.lanes = 2,\n+\t.mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |\n+\t\t MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,\n+\t.format = MIPI_DSI_FMT_RGB888,\n+\t.init_sequence = waveshare_5_5_inch_a_init_sequence,\n+};\n+\n static int hx8394_disable(struct drm_panel *panel)\n {\n \tstruct hx8394 *ctx = panel_to_hx8394(panel);\n@@ -815,6 +1057,8 @@ static const struct of_device_id hx8394_of_match[] = {\n \t{ .compatible = \"huiling,hl055fhav028c\", .data = &hl055fhav028c_desc },\n \t{ .compatible = \"powkiddy,x55-panel\", .data = &powkiddy_x55_desc },\n \t{ .compatible = \"microchip,ac40t08a-mipi-panel\", .data = &mchp_ac40t08a_desc },\n+\t{ .compatible = \"waveshare,5.0-dsi-touch-a\", .data = &waveshare_5_0_inch_a_desc },\n+\t{ .compatible = \"waveshare,5.5-dsi-touch-a\", .data = &waveshare_5_5_inch_a_desc },\n \t{ /* sentinel */ }\n };\n MODULE_DEVICE_TABLE(of, hx8394_of_match);\n","prefixes":["v3","10/21"]}