{"id":2222714,"url":"http://patchwork.ozlabs.org/api/patches/2222714/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260413140339.16238-3-cjd@cjdns.fr/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260413140339.16238-3-cjd@cjdns.fr>","list_archive_url":null,"date":"2026-04-13T14:03:39","name":"[v5,2/2] PCI: mediatek: Add support for EcoNet EN7528 SoC","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"a4be265eb984bf11e7e07c35096630f2cfdcd4a8","submitter":{"id":66262,"url":"http://patchwork.ozlabs.org/api/people/66262/?format=json","name":"Caleb James DeLisle","email":"cjd@cjdns.fr"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260413140339.16238-3-cjd@cjdns.fr/mbox/","series":[{"id":499709,"url":"http://patchwork.ozlabs.org/api/series/499709/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=499709","date":"2026-04-13T14:03:37","name":"PCI: mediatek: Add support for EcoNet SoCs","version":5,"mbox":"http://patchwork.ozlabs.org/series/499709/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222714/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222714/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=cjdns.fr header.i=@cjdns.fr header.a=rsa-sha256\n header.s=dkim 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h=from:subject:date:message-id:to:cc:mime-version:\n\t content-transfer-encoding:in-reply-to:references;\n\tbh=GdKZudBiZWRmnj2Q8xLAe5Ktsw/srDvDPRU3HuRREMc=;\n\tb=A4Yk1ABGxWLdq40Gvch9gUgy3szNqMcS5sYkVGBWDOnj4Nwan2XZP22vijpjyuVRBjDhqB\n\t3G1ZCKZPIg4V4m5YvBV354jG7tjV5X2AxfKcElxeT3ZZf2R/vaoLVaq1XoeoE0yykz2Mvq\n\tLFeJ1k6NgjymqkhJlyrnvM9q30oM3Hp3DGYSbAVz77pCYDk95kEB9BBg/osYwb2V91+F+Y\n\tGcbc4F8O4Eve/+A+iv75RxLZf4E3swTCpoGZ+oHXSr0aFPHsrLsRpJ4E8A6ZcWdua8J8RW\n\tdCxubAeiJY3/3d4Ko0VMUfcralaaf0UBQJ1EyHRl9pdQBD2HreeL/wsb7sMHEA==","From":"Caleb James DeLisle ","To":"linux-pci@vger.kernel.org","Cc":"linux-mips@vger.kernel.org,\n\tnaseefkm@gmail.com,\n\tryder.lee@mediatek.com,\n\thelgaas@kernel.org,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\trobh@kernel.org,\n\tkrzk+dt@kernel.org,\n\tconor+dt@kernel.org,\n\tmatthias.bgg@gmail.com,\n\tangelogioacchino.delregno@collabora.com,\n\tansuelsmth@gmail.com,\n\tlinux-mediatek@lists.infradead.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tCaleb James DeLisle ","Subject":"[PATCH v5 2/2] PCI: mediatek: Add support for EcoNet EN7528 SoC","Date":"Mon, 13 Apr 2026 14:03:39 +0000","Message-Id":"<20260413140339.16238-3-cjd@cjdns.fr>","In-Reply-To":"<20260413140339.16238-1-cjd@cjdns.fr>","References":"<20260413140339.16238-1-cjd@cjdns.fr>","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Last-TLS-Session-Version":"TLSv1.3"},"content":"Add support for the PCIe present on the EcoNet EN7528 (and EN751221) SoCs.\n\nThese SoCs have a mix of Gen1 and Gen2 capable ports, but the Gen2 ports\nrequire re-training after startup.\n\nCo-developed-by: Ahmed Naseef \nSigned-off-by: Ahmed Naseef \nSigned-off-by: Caleb James DeLisle \n---\n drivers/pci/controller/Kconfig | 2 +-\n drivers/pci/controller/pcie-mediatek.c | 133 +++++++++++++++++++++++++\n 2 files changed, 134 insertions(+), 1 deletion(-)","diff":"diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig\nindex 686349e09cd3..5808d5e407fd 100644\n--- a/drivers/pci/controller/Kconfig\n+++ b/drivers/pci/controller/Kconfig\n@@ -209,7 +209,7 @@ config PCI_MVEBU\n \n config PCIE_MEDIATEK\n \ttristate \"MediaTek PCIe controller\"\n-\tdepends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST\n+\tdepends on ARCH_AIROHA || ARCH_MEDIATEK || ECONET || COMPILE_TEST\n \tdepends on OF\n \tdepends on PCI_MSI\n \tselect IRQ_MSI_LIB\ndiff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c\nindex 75722524fe74..915a35825ce1 100644\n--- a/drivers/pci/controller/pcie-mediatek.c\n+++ b/drivers/pci/controller/pcie-mediatek.c\n@@ -7,6 +7,7 @@\n *\t Honghui Zhang \n */\n \n+#include \n #include \n #include \n #include \n@@ -14,6 +15,7 @@\n #include \n #include \n #include \n+#include \n #include \n #include \n #include \n@@ -77,6 +79,7 @@\n \n #define PCIE_CONF_VEND_ID\t0x100\n #define PCIE_CONF_DEVICE_ID\t0x102\n+#define PCIE_CONF_REV_CLASS\t0x104\n #define PCIE_CONF_CLASS_ID\t0x106\n \n #define PCIE_INT_MASK\t\t0x420\n@@ -89,6 +92,11 @@\n #define MSI_MASK\t\tBIT(23)\n #define MTK_MSI_IRQS_NUM\t32\n \n+#define EN7528_HOST_MODE\t0x00804201\n+#define EN7528_LINKUP_REG\t0x50\n+#define EN7528_RC0_LINKUP\tBIT(1)\n+#define EN7528_RC1_LINKUP\tBIT(2)\n+\n #define PCIE_AHB_TRANS_BASE0_L\t0x438\n #define PCIE_AHB_TRANS_BASE0_H\t0x43c\n #define AHB2PCIE_SIZE(x)\t((x) & GENMASK(4, 0))\n@@ -148,12 +156,15 @@ struct mtk_pcie_port;\n * @MTK_PCIE_FIX_DEVICE_ID: host's device ID needed to be fixed\n * @MTK_PCIE_NO_MSI: Bridge has no MSI support, and relies on an external block\n * @MTK_PCIE_SKIP_RSTB: Skip calling RSTB bits on PCIe probe\n+ * @MTK_PCIE_RETRAIN: Re-train link to bridge after startup because some\n+ * Gen2-capable devices start as Gen1.\n */\n enum mtk_pcie_quirks {\n \tMTK_PCIE_FIX_CLASS_ID = BIT(0),\n \tMTK_PCIE_FIX_DEVICE_ID = BIT(1),\n \tMTK_PCIE_NO_MSI = BIT(2),\n \tMTK_PCIE_SKIP_RSTB = BIT(3),\n+\tMTK_PCIE_RETRAIN = BIT(4),\n };\n \n /**\n@@ -753,6 +764,80 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)\n \treturn 0;\n }\n \n+static int mtk_pcie_startup_port_en7528(struct mtk_pcie_port *port)\n+{\n+\tstruct mtk_pcie *pcie = port->pcie;\n+\tstruct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);\n+\tstruct resource *mem = NULL;\n+\tstruct resource_entry *entry;\n+\tu32 val, link_mask;\n+\tint err;\n+\n+\tentry = resource_list_first_type(&host->windows, IORESOURCE_MEM);\n+\tif (entry)\n+\t\tmem = entry->res;\n+\tif (!mem)\n+\t\treturn -EINVAL;\n+\n+\tif (!pcie->cfg) {\n+\t\tdev_err(pcie->dev, \"EN7528: pciecfg syscon not available\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Assert all reset signals */\n+\twritel(0, port->base + PCIE_RST_CTRL);\n+\n+\t/*\n+\t * Enable PCIe link down reset, if link status changed from link up to\n+\t * link down, this will reset MAC control registers and configuration\n+\t * space.\n+\t */\n+\twritel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);\n+\n+\tmsleep(PCIE_T_PVPERL_MS);\n+\n+\t/* De-assert PHY, PE, PIPE, MAC and configuration reset */\n+\tval = readl(port->base + PCIE_RST_CTRL);\n+\tval |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |\n+\t PCIE_MAC_SRSTB | PCIE_CRSTB;\n+\twritel(val, port->base + PCIE_RST_CTRL);\n+\n+\twritel(PCIE_CLASS_CODE | PCIE_REVISION_ID,\n+\t port->base + PCIE_CONF_REV_CLASS);\n+\twritel(EN7528_HOST_MODE, port->base);\n+\n+\tlink_mask = (port->slot == 0) ? EN7528_RC0_LINKUP : EN7528_RC1_LINKUP;\n+\n+\t/* 100ms timeout value should be enough for Gen1/2 training */\n+\terr = regmap_read_poll_timeout(pcie->cfg, EN7528_LINKUP_REG, val,\n+\t\t\t\t !!(val & link_mask), 20,\n+\t\t\t\t PCI_PM_D3COLD_WAIT * USEC_PER_MSEC);\n+\tif (err) {\n+\t\tdev_err(pcie->dev, \"EN7528: port%d link timeout\\n\", port->slot);\n+\t\treturn -ETIMEDOUT;\n+\t}\n+\n+\t/* Activate INTx interrupts */\n+\tval = readl(port->base + PCIE_INT_MASK);\n+\tval &= ~INTX_MASK;\n+\twritel(val, port->base + PCIE_INT_MASK);\n+\n+\tif (IS_ENABLED(CONFIG_PCI_MSI))\n+\t\tmtk_pcie_enable_msi(port);\n+\n+\t/* Set AHB to PCIe translation windows */\n+\tval = lower_32_bits(mem->start) |\n+\t AHB2PCIE_SIZE(fls(resource_size(mem)));\n+\twritel(val, port->base + PCIE_AHB_TRANS_BASE0_L);\n+\n+\tval = upper_32_bits(mem->start);\n+\twritel(val, port->base + PCIE_AHB_TRANS_BASE0_H);\n+\n+\twritel(WIN_ENABLE, port->base + PCIE_AXI_WINDOW0);\n+\n+\treturn 0;\n+}\n+\n static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus,\n \t\t\t\t unsigned int devfn, int where)\n {\n@@ -1149,6 +1234,46 @@ static int mtk_pcie_probe(struct platform_device *pdev)\n \tif (err)\n \t\tgoto put_resources;\n \n+\t/* EN7528 PCIe initially comes up as Gen1 even if Gen2 is supported.\n+\t * The cannonical way to achieve Gen2 is to re-train the link\n+\t * immediately after setup. However, to save a lot of duplicated code\n+\t * we use pcie_retrain_link() which is usable once we have the pci_dev\n+\t * struct for the bridge, i.e. after pci_host_probe(). */\n+\tif (pcie->soc->quirks & MTK_PCIE_RETRAIN) {\n+\t\tint slot = of_get_pci_domain_nr(dev->of_node);\n+\t\tstruct pci_dev *rc = NULL;\n+\t\tint ret = -ENOENT;\n+\n+\t\tif (slot >= 0)\n+\t\t\trc = pci_get_slot(host->bus, PCI_DEVFN(slot, 0));\n+\n+\t\tif (rc) {\n+\t\t\tret = -EOPNOTSUPP;\n+\n+\t\t\t/* pcie_retrain_link() is not an exported symbol but\n+\t\t\t * this driver supports being built as a loadable\n+\t\t\t * module. Someone using this on an EN7528 should make\n+\t\t\t * it builtin, or accept Gen1 PCI. */\n+#if IS_BUILTIN(CONFIG_PCIE_MEDIATEK)\n+\t\t\tret = pcie_retrain_link(rc, true);\n+#endif\n+\t\t}\n+\n+\t\tif (ret) {\n+\t\t\tdev_info(dev, \"port%d failed to retrain %pe\\n\", slot,\n+\t\t\t\t ERR_PTR(ret));\n+\t\t} else {\n+\t\t\tu16 lnksta;\n+\t\t\tu32 speed;\n+\n+\t\t\tpcie_capability_read_word(rc, PCI_EXP_LNKSTA, &lnksta);\n+\t\t\tspeed = lnksta & PCI_EXP_LNKSTA_CLS;\n+\n+\t\t\tdev_info(dev, \"port%d link retrained, speed %s\\n\", slot,\n+\t\t\t\t pci_speed_string(pcie_link_speed[speed]));\n+\t\t}\n+\t}\n+\n \treturn 0;\n \n put_resources:\n@@ -1264,8 +1389,16 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = {\n \t.quirks = MTK_PCIE_FIX_CLASS_ID | MTK_PCIE_FIX_DEVICE_ID,\n };\n \n+static const struct mtk_pcie_soc mtk_pcie_soc_en7528 = {\n+\t.ops = &mtk_pcie_ops_v2,\n+\t.startup = mtk_pcie_startup_port_en7528,\n+\t.setup_irq = mtk_pcie_setup_irq,\n+\t.quirks = MTK_PCIE_RETRAIN,\n+};\n+\n static const struct of_device_id mtk_pcie_ids[] = {\n \t{ .compatible = \"airoha,an7583-pcie\", .data = &mtk_pcie_soc_an7583 },\n+\t{ .compatible = \"econet,en7528-pcie\", .data = &mtk_pcie_soc_en7528 },\n \t{ .compatible = \"mediatek,mt2701-pcie\", .data = &mtk_pcie_soc_v1 },\n \t{ .compatible = \"mediatek,mt7623-pcie\", .data = &mtk_pcie_soc_v1 },\n \t{ .compatible = \"mediatek,mt2712-pcie\", .data = &mtk_pcie_soc_mt2712 },\n","prefixes":["v5","2/2"]}