{"id":2222619,"url":"http://patchwork.ozlabs.org/api/patches/2222619/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260413073737.986219-14-gaurav.sharma_7@nxp.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260413073737.986219-14-gaurav.sharma_7@nxp.com>","list_archive_url":null,"date":"2026-04-13T07:37:35","name":"[PATCHv5,13/15] hw/arm/fsl-imx8mm: Adding support for ENET ethernet controller","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"683768ad8b670913c1bd26ef0a6454ef1433d667","submitter":{"id":92057,"url":"http://patchwork.ozlabs.org/api/people/92057/?format=json","name":"Gaurav Sharma","email":"gaurav.sharma_7@nxp.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260413073737.986219-14-gaurav.sharma_7@nxp.com/mbox/","series":[{"id":499658,"url":"http://patchwork.ozlabs.org/api/series/499658/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499658","date":"2026-04-13T07:37:27","name":"Adding comprehensive support for i.MX8MM EVK board","version":1,"mbox":"http://patchwork.ozlabs.org/series/499658/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222619/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222619/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":"legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Mon, 13 Apr 2026 03:38:06 -0400","from inva020.nxp.com (localhost [127.0.0.1])\n by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 345821A15A3;\n Mon, 13 Apr 2026 09:37:46 +0200 (CEST)","from aprdc01srsp001v.ap-rdc01.nxp.com\n (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16])\n by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id F385F1A1598;\n Mon, 13 Apr 2026 09:37:45 +0200 (CEST)","from lsv031015.swis.in-blr01.nxp.com\n (lsv031015.swis.in-blr01.nxp.com [10.12.177.77])\n by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 772791802228;\n Mon, 13 Apr 2026 15:37:45 +0800 (+08)"],"From":"Gaurav Sharma ","To":"qemu-devel@nongnu.org","Cc":"pbonzini@redhat.com, peter.maydell@linaro.org,\n Gaurav Sharma ","Subject":"[PATCHv5 13/15] hw/arm/fsl-imx8mm: Adding support for ENET ethernet\n controller","Date":"Mon, 13 Apr 2026 13:07:35 +0530","Message-Id":"<20260413073737.986219-14-gaurav.sharma_7@nxp.com>","X-Mailer":"git-send-email 2.34.1","In-Reply-To":"<20260413073737.986219-1-gaurav.sharma_7@nxp.com>","References":"<20260413073737.986219-1-gaurav.sharma_7@nxp.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Virus-Scanned":"ClamAV using ClamSMTP","Received-SPF":"pass client-ip=92.121.34.13;\n envelope-from=gaurav.sharma_7@nxp.com; helo=inva020.nxp.com","X-Spam_score_int":"-41","X-Spam_score":"-4.2","X-Spam_bar":"----","X-Spam_report":"(-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"It enables emulation of ENET ethernet controller in iMX8MM\nEnables testing and debugging of network dependent drivers\nAdded ENET MAC IRQ lines\n\nReviewed-by: Peter Maydell \nSigned-off-by: Gaurav Sharma \n---\n hw/arm/Kconfig | 1 +\n hw/arm/fsl-imx8mm.c | 24 ++++++++++++++++++++++++\n hw/arm/imx8mm-evk.c | 1 +\n include/hw/arm/fsl-imx8mm.h | 8 ++++++++\n 4 files changed, 34 insertions(+)","diff":"diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig\nindex f84bf725be..4095351490 100644\n--- a/hw/arm/Kconfig\n+++ b/hw/arm/Kconfig\n@@ -634,6 +634,7 @@ config FSL_IMX8MM\n select FSL_IMX8MP_ANALOG\n select FSL_IMX8MP_CCM\n select IMX\n+ select IMX_FEC\n select IMX_I2C\n select OR_IRQ\n select SDHCI\ndiff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c\nindex 613996cfec..a41837a4e8 100644\n--- a/hw/arm/fsl-imx8mm.c\n+++ b/hw/arm/fsl-imx8mm.c\n@@ -212,6 +212,8 @@ static void fsl_imx8mm_init(Object *obj)\n object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT);\n }\n \n+ object_initialize_child(obj, \"eth0\", &s->enet, TYPE_IMX_ENET);\n+\n object_initialize_child(obj, \"pcie\", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);\n object_initialize_child(obj, \"pcie_phy\", &s->pcie_phy,\n TYPE_FSL_IMX8M_PCIE_PHY);\n@@ -547,6 +549,21 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n qdev_get_gpio_in(gicdev, spi_table[i].irq));\n }\n \n+ /* ENET1 */\n+ object_property_set_uint(OBJECT(&s->enet), \"phy-num\", s->phy_num,\n+ &error_abort);\n+ object_property_set_uint(OBJECT(&s->enet), \"tx-ring-num\", 3, &error_abort);\n+ qemu_configure_nic_device(DEVICE(&s->enet), true, NULL);\n+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->enet), errp)) {\n+ return;\n+ }\n+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->enet), 0,\n+ fsl_imx8mm_memmap[FSL_IMX8MM_ENET1].addr);\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->enet), 0,\n+ qdev_get_gpio_in(gicdev, FSL_IMX8MM_ENET1_MAC_IRQ));\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->enet), 1,\n+ qdev_get_gpio_in(gicdev, FSL_IMX6_ENET1_MAC_1588_IRQ));\n+\n /* SNVS */\n if (!sysbus_realize(SYS_BUS_DEVICE(&s->snvs), errp)) {\n return;\n@@ -610,6 +627,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n case FSL_IMX8MM_GPIO1 ... FSL_IMX8MM_GPIO5:\n case FSL_IMX8MM_GPT1 ... FSL_IMX8MM_GPT6:\n \tcase FSL_IMX8MM_ECSPI1 ... FSL_IMX8MM_ECSPI3:\n+ case FSL_IMX8MM_ENET1:\n case FSL_IMX8MM_I2C1 ... FSL_IMX8MM_I2C4:\n case FSL_IMX8MM_PCIE1:\n case FSL_IMX8MM_PCIE_PHY1:\n@@ -631,10 +649,16 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n }\n }\n \n+static const Property fsl_imx8mm_properties[] = {\n+ DEFINE_PROP_UINT32(\"fec1-phy-num\", FslImx8mmState, phy_num, 0),\n+ DEFINE_PROP_BOOL(\"fec1-phy-connected\", FslImx8mmState, phy_connected, true),\n+};\n+\n static void fsl_imx8mm_class_init(ObjectClass *oc, const void *data)\n {\n DeviceClass *dc = DEVICE_CLASS(oc);\n \n+ device_class_set_props(dc, fsl_imx8mm_properties);\n dc->realize = fsl_imx8mm_realize;\n \n dc->desc = \"i.MX 8MM SoC\";\ndiff --git a/hw/arm/imx8mm-evk.c b/hw/arm/imx8mm-evk.c\nindex d1cc69dccb..f43ae21f18 100644\n--- a/hw/arm/imx8mm-evk.c\n+++ b/hw/arm/imx8mm-evk.c\n@@ -79,6 +79,7 @@ static void imx8mm_evk_init(MachineState *machine)\n \n s = FSL_IMX8MM(object_new_with_props(TYPE_FSL_IMX8MM, OBJECT(machine),\n \"soc\", &error_fatal, NULL));\n+ object_property_set_uint(OBJECT(s), \"fec1-phy-num\", 1, &error_fatal);\n sysbus_realize_and_unref(SYS_BUS_DEVICE(s), &error_fatal);\n \n memory_region_add_subregion(get_system_memory(), FSL_IMX8MM_RAM_START,\ndiff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h\nindex 607ac86666..c212b6a7a7 100644\n--- a/include/hw/arm/fsl-imx8mm.h\n+++ b/include/hw/arm/fsl-imx8mm.h\n@@ -18,6 +18,7 @@\n #include \"hw/misc/imx7_snvs.h\"\n #include \"hw/misc/imx8mp_analog.h\"\n #include \"hw/misc/imx8mp_ccm.h\"\n+#include \"hw/net/imx_fec.h\"\n #include \"hw/or-irq.h\"\n #include \"hw/pci-host/designware.h\"\n #include \"hw/pci-host/fsl_imx8m_phy.h\"\n@@ -60,11 +61,15 @@ struct FslImx8mmState {\n IMXI2CState i2c[FSL_IMX8MM_NUM_I2CS];\n IMXSerialState uart[FSL_IMX8MM_NUM_UARTS];\n MemoryRegion ocram;\n+ IMXFECState enet;\n SDHCIState usdhc[FSL_IMX8MM_NUM_USDHCS];\n IMX2WdtState wdt[FSL_IMX8MM_NUM_WDTS];\n DesignwarePCIEHost pcie;\n FslImx8mPciePhyState pcie_phy;\n OrIRQState gpt5_gpt6_irq;\n+\n+ uint32_t phy_num;\n+ bool phy_connected;\n };\n \n enum FslImx8mmMemoryRegions {\n@@ -218,6 +223,9 @@ enum FslImx8mmIrqs {\n FSL_IMX8MM_WDOG2_IRQ = 79,\n FSL_IMX8MM_WDOG3_IRQ = 10,\n \n+ FSL_IMX8MM_ENET1_MAC_IRQ = 118,\n+ FSL_IMX6_ENET1_MAC_1588_IRQ = 121,\n+\n FSL_IMX8MM_PCI_INTA_IRQ = 122,\n FSL_IMX8MM_PCI_INTB_IRQ = 123,\n FSL_IMX8MM_PCI_INTC_IRQ = 124,\n","prefixes":["PATCHv5","13/15"]}