{"id":2222468,"url":"http://patchwork.ozlabs.org/api/patches/2222468/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/99be0e0e0d43c77389dd076d079b195844817076.1775959096.git.chao.liu.zevorn@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<99be0e0e0d43c77389dd076d079b195844817076.1775959096.git.chao.liu.zevorn@gmail.com>","list_archive_url":null,"date":"2026-04-12T02:20:20","name":"[v6,3/7] target/riscv: add sdext Debug Mode helpers","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"3b962898eb5ace68e340bdec2cecf2523326d48a","submitter":{"id":92265,"url":"http://patchwork.ozlabs.org/api/people/92265/?format=json","name":"Chao Liu","email":"chao.liu.zevorn@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/99be0e0e0d43c77389dd076d079b195844817076.1775959096.git.chao.liu.zevorn@gmail.com/mbox/","series":[{"id":499584,"url":"http://patchwork.ozlabs.org/api/series/499584/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499584","date":"2026-04-12T02:20:20","name":"riscv: add initial sdext support","version":6,"mbox":"http://patchwork.ozlabs.org/series/499584/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222468/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222468/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=dRfa+4jy;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-qv1-xf41.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"RISC-V Debug Specification:\nhttps://github.com/riscv/riscv-debug-spec/releases/tag/1.0\n\nAdd helpers to enter/leave Debug Mode and to update dpc/dcsr.\nModel resume without a Debug Module by leaving Debug Mode at\ncpu_exec_enter and continuing from dpc.\n\nSigned-off-by: Chao Liu \nReviewed-by: Daniel Henrique Barboza \nTested-by: Tao Tang \n---\n target/riscv/cpu.h | 3 ++\n target/riscv/cpu_helper.c | 84 ++++++++++++++++++++++++++++++++++++++\n target/riscv/debug.c | 5 +++\n target/riscv/tcg/tcg-cpu.c | 14 +++++++\n 4 files changed, 106 insertions(+)","diff":"diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h\nindex 2a265faae5..62732957a4 100644\n--- a/target/riscv/cpu.h\n+++ b/target/riscv/cpu.h\n@@ -624,6 +624,9 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,\n char *riscv_isa_string(RISCVCPU *cpu);\n int riscv_cpu_max_xlen(RISCVCPUClass *mcc);\n bool riscv_cpu_option_set(const char *optname);\n+void riscv_cpu_enter_debug_mode(CPURISCVState *env, target_ulong pc,\n+ uint32_t cause);\n+void riscv_cpu_leave_debug_mode(CPURISCVState *env);\n \n #ifndef CONFIG_USER_ONLY\n void riscv_cpu_do_interrupt(CPUState *cpu);\ndiff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c\nindex 659150c646..0ff11a45de 100644\n--- a/target/riscv/cpu_helper.c\n+++ b/target/riscv/cpu_helper.c\n@@ -136,6 +136,90 @@ bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt)\n #endif\n }\n \n+#ifndef CONFIG_USER_ONLY\n+static bool riscv_sdext_enabled(CPURISCVState *env)\n+{\n+ return riscv_cpu_cfg(env)->ext_sdext;\n+}\n+#endif\n+\n+void riscv_cpu_enter_debug_mode(CPURISCVState *env, target_ulong pc,\n+ uint32_t cause)\n+{\n+#ifndef CONFIG_USER_ONLY\n+ if (!riscv_sdext_enabled(env)) {\n+ return;\n+ }\n+\n+ env->debug_mode = true;\n+ env->dpc = pc & get_xepc_mask(env);\n+ env->dcsr &= ~(DCSR_CAUSE_MASK | DCSR_PRV_MASK | DCSR_V);\n+ env->dcsr |= ((target_ulong)(cause & 0x7)) << DCSR_CAUSE_SHIFT;\n+ env->dcsr |= env->priv & DCSR_PRV_MASK;\n+ if (env->virt_enabled && riscv_has_ext(env, RVH)) {\n+ env->dcsr |= DCSR_V;\n+ }\n+\n+ if (env_archcpu(env)->cfg.ext_zicfilp) {\n+ if (env->elp) {\n+ env->dcsr |= DCSR_PELP;\n+ } else {\n+ env->dcsr &= ~DCSR_PELP;\n+ }\n+ env->elp = false;\n+ }\n+#endif\n+}\n+\n+void riscv_cpu_leave_debug_mode(CPURISCVState *env)\n+{\n+#ifndef CONFIG_USER_ONLY\n+ if (!riscv_sdext_enabled(env)) {\n+ return;\n+ }\n+\n+ target_ulong new_priv = env->dcsr & DCSR_PRV_MASK;\n+ bool new_virt = riscv_has_ext(env, RVH) && (env->dcsr & DCSR_V);\n+\n+ if (new_priv > PRV_M) {\n+ new_priv = PRV_M;\n+ }\n+ if (new_priv == PRV_M) {\n+ new_virt = false;\n+ }\n+\n+ if (new_priv == PRV_S && !riscv_has_ext(env, RVS)) {\n+ new_priv = PRV_M;\n+ new_virt = false;\n+ } else if (new_priv == PRV_U && !riscv_has_ext(env, RVU)) {\n+ new_priv = riscv_has_ext(env, RVS) ? PRV_S : PRV_M;\n+ new_virt = false;\n+ }\n+\n+ env->debug_mode = false;\n+ riscv_cpu_set_mode(env, new_priv, new_virt);\n+\n+ if (env_archcpu(env)->cfg.ext_zicfilp) {\n+ env->elp = cpu_get_fcfien(env) && (env->dcsr & DCSR_PELP);\n+ env->dcsr &= ~DCSR_PELP;\n+ }\n+\n+ if (new_priv != PRV_M) {\n+ env->mstatus = set_field(env->mstatus, MSTATUS_MPRV, 0);\n+ }\n+\n+ if (env_archcpu(env)->cfg.ext_smdbltrp && new_priv != PRV_M) {\n+ env->mstatus = set_field(env->mstatus, MSTATUS_MDT, 0);\n+ }\n+ if (env_archcpu(env)->cfg.ext_ssdbltrp && (new_priv == PRV_U || new_virt)) {\n+ env->mstatus = set_field(env->mstatus, MSTATUS_SDT, 0);\n+ if (new_virt && new_priv == PRV_U) {\n+ env->vsstatus = set_field(env->vsstatus, MSTATUS_SDT, 0);\n+ }\n+ }\n+#endif\n+}\n+\n RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env)\n {\n #ifndef CONFIG_USER_ONLY\ndiff --git a/target/riscv/debug.c b/target/riscv/debug.c\nindex 5664466749..5877a60c50 100644\n--- a/target/riscv/debug.c\n+++ b/target/riscv/debug.c\n@@ -927,6 +927,11 @@ void riscv_cpu_debug_excp_handler(CPUState *cs)\n RISCVCPU *cpu = RISCV_CPU(cs);\n CPURISCVState *env = &cpu->env;\n \n+ /* Triggers must not match or fire while in Debug Mode. */\n+ if (env->debug_mode) {\n+ return;\n+ }\n+\n if (cs->watchpoint_hit) {\n if (cs->watchpoint_hit->flags & BP_CPU) {\n do_trigger_action(env, DBG_ACTION_BP);\ndiff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c\nindex 0613450691..4b17fbb611 100644\n--- a/target/riscv/tcg/tcg-cpu.c\n+++ b/target/riscv/tcg/tcg-cpu.c\n@@ -266,6 +266,19 @@ static vaddr riscv_pointer_wrap(CPUState *cs, int mmu_idx,\n }\n return extract64(result, 0, 64 - pm_len);\n }\n+\n+static void riscv_cpu_exec_enter(CPUState *cs)\n+{\n+ RISCVCPU *cpu = RISCV_CPU(cs);\n+ CPURISCVState *env = &cpu->env;\n+\n+ if (!cpu->cfg.ext_sdext || !env->debug_mode) {\n+ return;\n+ }\n+ target_ulong pc = env->dpc;\n+ riscv_cpu_leave_debug_mode(env);\n+ env->pc = pc;\n+}\n #endif\n \n const TCGCPUOps riscv_tcg_ops = {\n@@ -282,6 +295,7 @@ const TCGCPUOps riscv_tcg_ops = {\n #ifndef CONFIG_USER_ONLY\n .tlb_fill = riscv_cpu_tlb_fill,\n .pointer_wrap = riscv_pointer_wrap,\n+ .cpu_exec_enter = riscv_cpu_exec_enter,\n .cpu_exec_interrupt = riscv_cpu_exec_interrupt,\n .cpu_exec_halt = riscv_cpu_has_work,\n .cpu_exec_reset = cpu_reset,\n","prefixes":["v6","3/7"]}