{"id":2221944,"url":"http://patchwork.ozlabs.org/api/patches/2221944/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260410-sdxi-base-v1-6-1d184cb5c60a@amd.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260410-sdxi-base-v1-6-1d184cb5c60a@amd.com>","list_archive_url":null,"date":"2026-04-10T13:07:16","name":"[06/23] dmaengine: sdxi: Allocate DMA pools","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"352b4f6e5cbed70b89bb63adba834e1621ac566b","submitter":{"id":91626,"url":"http://patchwork.ozlabs.org/api/people/91626/?format=json","name":"Nathan Lynch via B4 Relay","email":"devnull+nathan.lynch.amd.com@kernel.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260410-sdxi-base-v1-6-1d184cb5c60a@amd.com/mbox/","series":[{"id":499458,"url":"http://patchwork.ozlabs.org/api/series/499458/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=499458","date":"2026-04-10T13:07:10","name":"dmaengine: Smart Data Accelerator Interface (SDXI) basic support","version":1,"mbox":"http://patchwork.ozlabs.org/series/499458/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2221944/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221944/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=UaKoNb8T;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-52318-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"UaKoNb8T\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fsccK3p4pz1yGS\n\tfor ; Fri, 10 Apr 2026 23:10:41 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 07F7430557E8\n\tfor ; Fri, 10 Apr 2026 13:07:57 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 8C1273A7842;\n\tFri, 10 Apr 2026 13:07:50 +0000 (UTC)","from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A33B344031;\n\tFri, 10 Apr 2026 13:07:50 +0000 (UTC)","by smtp.kernel.org (Postfix) with ESMTPS id D6646C2BCB2;\n\tFri, 10 Apr 2026 13:07:49 +0000 (UTC)","from aws-us-west-2-korg-lkml-1.web.codeaurora.org\n (localhost.localdomain [127.0.0.1])\n\tby smtp.lore.kernel.org (Postfix) with ESMTP id CDDE8F4485B;\n\tFri, 10 Apr 2026 13:07:49 +0000 (UTC)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1775826470; cv=none;\n b=I+zH34Q92z+w9BnSZftKj4wNKnmtUYpgJdpvWNlf2IHsN/Y3KDr/6m1cBPzdKOYdu+oJyNj2xzkl4JJbLIaJlXhZvx5Zq8F9U6H5n2sLf8jHjNgNuWLnFr9KrxqXzPS8kYIVHxyS7pFHk+sXXVe9foT9p8Mpl4xIYdMsIZbU55s=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1775826470; c=relaxed/simple;\n\tbh=hpysSDdkkiKhjp1o0gRPLKO/3dcD0MkxiD0l9bXNbKM=;\n\th=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References:\n\t In-Reply-To:To:Cc;\n b=t9p9MP3XcwgT71GX8gitOUtOV89kPOTIzX+22s14TKmbAyjTzdWEjG0mPuP1RqTZ9xy09t2sYMCkigunBHdPtmw0BYEW0/9m5IZ4O1cfiSVljuSFOGwsd/gyVgo35qYwtyaqRPaaKPS9ds0aDyJD3QwrE/zTclGpm8Ew3pp82Ck=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=UaKoNb8T; arc=none smtp.client-ip=10.30.226.201","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1775826469;\n\tbh=hpysSDdkkiKhjp1o0gRPLKO/3dcD0MkxiD0l9bXNbKM=;\n\th=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From;\n\tb=UaKoNb8TNtZJCPfCswc+cr5n/qvXntnz5+p4YHzX5IwYTxGQpqhQ4p77LWsQhTCmF\n\t oHufQvFzzduxAxD57Tkwp8h3oczupclbqm04fSs1qkQs8/rq/AXk1f+Xf0zk9fMadl\n\t tc4PjsRlVUw58Tkq8AfjHdyrpryFEjRXWXo5Q+mIpE6nhJlUBkGbZXmtFQDLQWAppY\n\t +fKy1Yh7JlfehmewWF6Biz3xm5iv3xMnzfLslgQvjA/abGEB7duCEUmlg7egq5hHAG\n\t /vdpFxunjL9Sd9FJNWioJvxy5oFROz2h/z5H+02t7jV01et9a2lfQ9v28sULmg5HR7\n\t Wup/Utnjtl9Dw==","From":"Nathan Lynch via B4 Relay ","Date":"Fri, 10 Apr 2026 08:07:16 -0500","Subject":"[PATCH 06/23] dmaengine: sdxi: Allocate DMA pools","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260410-sdxi-base-v1-6-1d184cb5c60a@amd.com>","References":"<20260410-sdxi-base-v1-0-1d184cb5c60a@amd.com>","In-Reply-To":"<20260410-sdxi-base-v1-0-1d184cb5c60a@amd.com>","To":"Vinod Koul ","Cc":"Wei Huang ,\n Mario Limonciello ,\n Bjorn Helgaas ,\n Jonathan Cameron ,\n Stephen Bates , PradeepVineshReddy.Kodamati@amd.com,\n John.Kariuki@amd.com, linux-pci@vger.kernel.org,\n linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,\n Nathan Lynch ","X-Mailer":"b4 0.15.2","X-Developer-Signature":"v=1; a=ed25519-sha256; t=1775826467; l=4160;\n i=nathan.lynch@amd.com; s=20260410; h=from:subject:message-id;\n bh=yYsDKehkM4Su6gA/w8eyy9OZyEDpuCpJ6inX5B52w14=;\n b=wAVdujdNT6YNKgQ26NGu8syqu1ZYOAPoCK0Kpv5qHmpAE5Hs22ujLAZMKUrpY5EKAAEvIN38+\n f/3+JTAETKODXyk/g9POCTXV9E2qjlypR2KZ3oVphLIu4IzECrkwBiE","X-Developer-Key":"i=nathan.lynch@amd.com; a=ed25519;\n pk=PK4ozhq+/z9/2Jl5rgDmvHa9raVomv79qM8p1RAFpEw=","X-Endpoint-Received":"by B4 Relay for nathan.lynch@amd.com/20260410 with\n auth_id=728","X-Original-From":"Nathan Lynch ","Reply-To":"nathan.lynch@amd.com"},"content":"From: Nathan Lynch \n\nEach SDXI context consists of several control structures in system\nmemory:\n\n* Descriptor ring\n* Access key (AKey) table\n* Context control block (CXT_CTL)\n* Context status block (CXT_STS)\n* Write index\n\nOf these, the write index, context control and context status blocks\nare small enough to justify DMA pools.\n\nSDXI descriptors may optionally have 32-byte completion status\nblocks (CST_BLK) associated with them that software can poll for\ncompletion.\n\nIntroduce the C structures for context control, context status, and\ncompletion status blocks. Create a DMA pool for each of these objects\nas well as write indexes during SDXI function initialization.\n\nCo-developed-by: Wei Huang \nSigned-off-by: Wei Huang \nSigned-off-by: Nathan Lynch \n---\n drivers/dma/sdxi/device.c | 34 +++++++++++++++++++++++++++++++++-\n drivers/dma/sdxi/hw.h | 28 ++++++++++++++++++++++++++++\n drivers/dma/sdxi/sdxi.h | 5 +++++\n 3 files changed, 66 insertions(+), 1 deletion(-)","diff":"diff --git a/drivers/dma/sdxi/device.c b/drivers/dma/sdxi/device.c\nindex 7e772ce81365..80bd1bbd9c7c 100644\n--- a/drivers/dma/sdxi/device.c\n+++ b/drivers/dma/sdxi/device.c\n@@ -9,6 +9,7 @@\n #include \n #include \n #include \n+#include \n #include \n #include \n \n@@ -188,6 +189,37 @@ static int sdxi_fn_activate(struct sdxi_dev *sdxi)\n \treturn 0;\n }\n \n+static int sdxi_create_dma_pool(struct sdxi_dev *sdxi, struct dma_pool **pool,\n+\t\t\t\tconst char *name, size_t size)\n+{\n+\t*pool = dmam_pool_create(name, sdxi_to_dev(sdxi), size, size, 0);\n+\treturn *pool ? 0 : -ENOMEM;\n+}\n+\n+static int sdxi_device_init(struct sdxi_dev *sdxi)\n+{\n+\tint err;\n+\n+\tif (sdxi_create_dma_pool(sdxi, &sdxi->write_index_pool,\n+\t\t\t\t \"Write_Index\", sizeof(__le64)))\n+\t\treturn -ENOMEM;\n+\tif (sdxi_create_dma_pool(sdxi, &sdxi->cxt_sts_pool,\n+\t\t\t\t \"CXT_STS\", sizeof(struct sdxi_cxt_sts)))\n+\t\treturn -ENOMEM;\n+\tif (sdxi_create_dma_pool(sdxi, &sdxi->cxt_ctl_pool,\n+\t\t\t\t \"CXT_CTL\", sizeof(struct sdxi_cxt_ctl)))\n+\t\treturn -ENOMEM;\n+\tif (sdxi_create_dma_pool(sdxi, &sdxi->cst_blk_pool,\n+\t\t\t\t \"CST_BLK\", sizeof(struct sdxi_cst_blk)))\n+\t\treturn -ENOMEM;\n+\n+\terr = sdxi_fn_activate(sdxi);\n+\tif (err)\n+\t\treturn err;\n+\n+\treturn 0;\n+}\n+\n int sdxi_register(struct device *dev, const struct sdxi_bus_ops *ops)\n {\n \tstruct sdxi_dev *sdxi;\n@@ -205,5 +237,5 @@ int sdxi_register(struct device *dev, const struct sdxi_bus_ops *ops)\n \tif (err)\n \t\treturn err;\n \n-\treturn sdxi_fn_activate(sdxi);\n+\treturn sdxi_device_init(sdxi);\n }\ndiff --git a/drivers/dma/sdxi/hw.h b/drivers/dma/sdxi/hw.h\nindex df520ca7792b..846c671c423f 100644\n--- a/drivers/dma/sdxi/hw.h\n+++ b/drivers/dma/sdxi/hw.h\n@@ -58,4 +58,32 @@ struct sdxi_cxt_L1_table {\n };\n static_assert(sizeof(struct sdxi_cxt_L1_table) == 4096);\n \n+/* SDXI 1.0 Table 3-4: Context Control (CXT_CTL) */\n+struct sdxi_cxt_ctl {\n+\t__le64 ds_ring_ptr;\n+\t__le32 ds_ring_sz;\n+\t__u8 rsvd_0[4];\n+\t__le64 cxt_sts_ptr;\n+\t__le64 write_index_ptr;\n+\t__u8 rsvd_1[32];\n+} __packed;\n+static_assert(sizeof(struct sdxi_cxt_ctl) == 64);\n+\n+/* SDXI 1.0 Table 3-5: Context Status (CXT_STS) */\n+struct sdxi_cxt_sts {\n+\t__u8 state;\n+\t__u8 misc0;\n+\t__u8 rsvd_0[6];\n+\t__le64 read_index;\n+} __packed;\n+static_assert(sizeof(struct sdxi_cxt_sts) == 16);\n+\n+/* SDXI 1.0 Table 6-4: CST_BLK (Completion Status Block) */\n+struct sdxi_cst_blk {\n+\t__le64 signal;\n+\t__le32 flags;\n+\t__u8 rsvd_0[20];\n+} __packed;\n+static_assert(sizeof(struct sdxi_cst_blk) == 32);\n+\n #endif /* DMA_SDXI_HW_H */\ndiff --git a/drivers/dma/sdxi/sdxi.h b/drivers/dma/sdxi/sdxi.h\nindex 185f58b725da..6cda60bb33c4 100644\n--- a/drivers/dma/sdxi/sdxi.h\n+++ b/drivers/dma/sdxi/sdxi.h\n@@ -46,6 +46,11 @@ struct sdxi_dev {\n \tstruct sdxi_cxt_L1_table *L1_table;\n \tdma_addr_t L1_dma;\n \n+\tstruct dma_pool *write_index_pool;\n+\tstruct dma_pool *cxt_sts_pool;\n+\tstruct dma_pool *cxt_ctl_pool;\n+\tstruct dma_pool *cst_blk_pool;\n+\n \tconst struct sdxi_bus_ops *bus_ops;\n };\n \n","prefixes":["06/23"]}