{"id":2221943,"url":"http://patchwork.ozlabs.org/api/patches/2221943/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260410-sdxi-base-v1-7-1d184cb5c60a@amd.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260410-sdxi-base-v1-7-1d184cb5c60a@amd.com>","list_archive_url":null,"date":"2026-04-10T13:07:17","name":"[07/23] dmaengine: sdxi: Allocate administrative context","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"984e308a0e31fcbd0df095fe00fc6995c6bba128","submitter":{"id":91626,"url":"http://patchwork.ozlabs.org/api/people/91626/?format=json","name":"Nathan Lynch via B4 Relay","email":"devnull+nathan.lynch.amd.com@kernel.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260410-sdxi-base-v1-7-1d184cb5c60a@amd.com/mbox/","series":[{"id":499458,"url":"http://patchwork.ozlabs.org/api/series/499458/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=499458","date":"2026-04-10T13:07:10","name":"dmaengine: Smart Data Accelerator Interface (SDXI) basic support","version":1,"mbox":"http://patchwork.ozlabs.org/series/499458/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2221943/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221943/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=c6OmW/hh;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260410-sdxi-base-v1-7-1d184cb5c60a@amd.com>","References":"<20260410-sdxi-base-v1-0-1d184cb5c60a@amd.com>","In-Reply-To":"<20260410-sdxi-base-v1-0-1d184cb5c60a@amd.com>","To":"Vinod Koul ","Cc":"Wei Huang ,\n Mario Limonciello ,\n Bjorn Helgaas ,\n Jonathan Cameron ,\n Stephen Bates , PradeepVineshReddy.Kodamati@amd.com,\n John.Kariuki@amd.com, linux-pci@vger.kernel.org,\n linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,\n Nathan Lynch ","X-Mailer":"b4 0.15.2","X-Developer-Signature":"v=1; a=ed25519-sha256; t=1775826467; l=9093;\n i=nathan.lynch@amd.com; s=20260410; h=from:subject:message-id;\n bh=5IR26H76UDlcFM7Wa9aSD6wT/Up6jQCxqaCJ4XRcXKE=;\n b=bCtQW+/DPZvbj0rP7gSVEu2yumHr14XsLG/TOWlXxjrAXvvrUz877kx+cK6+e85OHh8rOpsq7\n rG/snavaeMCD2V6oU4zNZI5XJkFEqkS1aAa7UC55GPOYvOHWOFCZSHf","X-Developer-Key":"i=nathan.lynch@amd.com; a=ed25519;\n pk=PK4ozhq+/z9/2Jl5rgDmvHa9raVomv79qM8p1RAFpEw=","X-Endpoint-Received":"by B4 Relay for nathan.lynch@amd.com/20260410 with\n auth_id=728","X-Original-From":"Nathan Lynch ","Reply-To":"nathan.lynch@amd.com"},"content":"From: Nathan Lynch \n\nCreate the control structure hierarchy in memory for the per-function\nadministrative context. Use devres to queue the corresponding cleanup\nsince the admin context is a device-scope resource. The context is\ninert for now; changes to follow will make it functional.\n\nCo-developed-by: Wei Huang \nSigned-off-by: Wei Huang \nSigned-off-by: Nathan Lynch \n---\n drivers/dma/sdxi/Makefile | 4 +-\n drivers/dma/sdxi/context.c | 128 +++++++++++++++++++++++++++++++++++++++++++++\n drivers/dma/sdxi/context.h | 54 +++++++++++++++++++\n drivers/dma/sdxi/device.c | 11 ++++\n drivers/dma/sdxi/hw.h | 43 +++++++++++++++\n drivers/dma/sdxi/sdxi.h | 2 +\n 6 files changed, 241 insertions(+), 1 deletion(-)","diff":"diff --git a/drivers/dma/sdxi/Makefile b/drivers/dma/sdxi/Makefile\nindex f84b87d53e27..2178f274831c 100644\n--- a/drivers/dma/sdxi/Makefile\n+++ b/drivers/dma/sdxi/Makefile\n@@ -1,6 +1,8 @@\n # SPDX-License-Identifier: GPL-2.0\n obj-$(CONFIG_SDXI) += sdxi.o\n \n-sdxi-objs += device.o\n+sdxi-objs += \\\n+\tcontext.o \\\n+\tdevice.o\n \n sdxi-$(CONFIG_PCI_MSI) += pci.o\ndiff --git a/drivers/dma/sdxi/context.c b/drivers/dma/sdxi/context.c\nnew file mode 100644\nindex 000000000000..0a6821992776\n--- /dev/null\n+++ b/drivers/dma/sdxi/context.c\n@@ -0,0 +1,128 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * SDXI context management\n+ *\n+ * Copyright Advanced Micro Devices, Inc.\n+ */\n+\n+#define pr_fmt(fmt) \"SDXI: \" fmt\n+\n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+\n+#include \"context.h\"\n+#include \"sdxi.h\"\n+\n+#define DEFAULT_DESC_RING_ENTRIES 1024\n+\n+enum {\n+\t/*\n+\t * The admin context always has ID 0. See SDXI 1.0 3.5\n+\t * Administrative Context (Context 0).\n+\t */\n+\tSDXI_ADMIN_CXT_ID = 0,\n+};\n+\n+/*\n+ * Free context and its resources. @cxt may be partially allocated but\n+ * must have ->sdxi set.\n+ */\n+static void sdxi_free_cxt(struct sdxi_cxt *cxt)\n+{\n+\tstruct sdxi_dev *sdxi = cxt->sdxi;\n+\tstruct sdxi_sq *sq = cxt->sq;\n+\n+\tif (cxt->cxt_ctl)\n+\t\tdma_pool_free(sdxi->cxt_ctl_pool, cxt->cxt_ctl,\n+\t\t\t cxt->cxt_ctl_dma);\n+\tif (cxt->akey_table)\n+\t\tdma_free_coherent(sdxi_to_dev(sdxi), sizeof(*cxt->akey_table),\n+\t\t\t\t cxt->akey_table, cxt->akey_table_dma);\n+\tif (sq && sq->write_index)\n+\t\tdma_pool_free(sdxi->write_index_pool, sq->write_index,\n+\t\t\t sq->write_index_dma);\n+\tif (sq && sq->cxt_sts)\n+\t\tdma_pool_free(sdxi->cxt_sts_pool, sq->cxt_sts, sq->cxt_sts_dma);\n+\tif (sq && sq->desc_ring)\n+\t\tdma_free_coherent(sdxi_to_dev(sdxi), sq->ring_size,\n+\t\t\t\t sq->desc_ring, sq->ring_dma);\n+\tkfree(cxt->sq);\n+\tkfree(cxt);\n+}\n+\n+DEFINE_FREE(sdxi_cxt, struct sdxi_cxt *, if (_T) sdxi_free_cxt(_T))\n+\n+/* Allocate a context and its control structure hierarchy in memory. */\n+static struct sdxi_cxt *sdxi_alloc_cxt(struct sdxi_dev *sdxi)\n+{\n+\tstruct device *dev = sdxi_to_dev(sdxi);\n+\tstruct sdxi_sq *sq;\n+\tstruct sdxi_cxt *cxt __free(sdxi_cxt) = kzalloc(sizeof(*cxt), GFP_KERNEL);\n+\n+\tif (!cxt)\n+\t\treturn NULL;\n+\n+\tcxt->sdxi = sdxi;\n+\n+\tcxt->sq = kzalloc_obj(*cxt->sq, GFP_KERNEL);\n+\tif (!cxt->sq)\n+\t\treturn NULL;\n+\n+\tcxt->akey_table = dma_alloc_coherent(dev, sizeof(*cxt->akey_table),\n+\t\t\t\t\t &cxt->akey_table_dma, GFP_KERNEL);\n+\tif (!cxt->akey_table)\n+\t\treturn NULL;\n+\n+\tcxt->cxt_ctl = dma_pool_zalloc(sdxi->cxt_ctl_pool, GFP_KERNEL,\n+\t\t\t\t &cxt->cxt_ctl_dma);\n+\tif (!cxt->cxt_ctl_dma)\n+\t\treturn NULL;\n+\n+\tsq = cxt->sq;\n+\n+\tsq->ring_entries = DEFAULT_DESC_RING_ENTRIES;\n+\tsq->ring_size = sq->ring_entries * sizeof(sq->desc_ring[0]);\n+\tsq->desc_ring = dma_alloc_coherent(dev, sq->ring_size, &sq->ring_dma,\n+\t\t\t\t\t GFP_KERNEL);\n+\tif (!sq->desc_ring)\n+\t\treturn NULL;\n+\n+\tsq->cxt_sts = dma_pool_zalloc(sdxi->cxt_sts_pool, GFP_KERNEL,\n+\t\t\t\t &sq->cxt_sts_dma);\n+\tif (!sq->cxt_sts)\n+\t\treturn NULL;\n+\n+\tsq->write_index = dma_pool_zalloc(sdxi->write_index_pool, GFP_KERNEL,\n+\t\t\t\t\t &sq->write_index_dma);\n+\tif (!sq->write_index)\n+\t\treturn NULL;\n+\n+\treturn_ptr(cxt);\n+}\n+\n+static void free_admin_cxt(void *ptr)\n+{\n+\tstruct sdxi_dev *sdxi = ptr;\n+\n+\tsdxi_free_cxt(sdxi->admin_cxt);\n+}\n+\n+int sdxi_admin_cxt_init(struct sdxi_dev *sdxi)\n+{\n+\tstruct sdxi_cxt *cxt __free(sdxi_cxt) = sdxi_alloc_cxt(sdxi);\n+\tif (!cxt)\n+\t\treturn -ENOMEM;\n+\n+\tcxt->id = SDXI_ADMIN_CXT_ID;\n+\tcxt->db = sdxi->dbs + cxt->id * sdxi->db_stride;\n+\n+\tsdxi->admin_cxt = no_free_ptr(cxt);\n+\n+\treturn devm_add_action_or_reset(sdxi_to_dev(sdxi), free_admin_cxt, sdxi);\n+}\ndiff --git a/drivers/dma/sdxi/context.h b/drivers/dma/sdxi/context.h\nnew file mode 100644\nindex 000000000000..800b4ead1dd9\n--- /dev/null\n+++ b/drivers/dma/sdxi/context.h\n@@ -0,0 +1,54 @@\n+/* SPDX-License-Identifier: GPL-2.0-only */\n+/*\n+ * Copyright Advanced Micro Devices, Inc.\n+ */\n+\n+#ifndef DMA_SDXI_CONTEXT_H\n+#define DMA_SDXI_CONTEXT_H\n+\n+#include \n+#include \n+\n+#include \"hw.h\"\n+#include \"sdxi.h\"\n+\n+/*\n+ * The size of the AKey table is flexible, from 4KB to 1MB. Always use\n+ * the minimum size for now.\n+ */\n+struct sdxi_akey_table {\n+\tstruct sdxi_akey_ent entry[SZ_4K / sizeof(struct sdxi_akey_ent)];\n+};\n+\n+/* Submission Queue */\n+struct sdxi_sq {\n+\tu32 ring_entries;\n+\tu32 ring_size;\n+\tstruct sdxi_desc *desc_ring;\n+\tdma_addr_t ring_dma;\n+\n+\t__le64 *write_index;\n+\tdma_addr_t write_index_dma;\n+\n+\tstruct sdxi_cxt_sts *cxt_sts;\n+\tdma_addr_t cxt_sts_dma;\n+};\n+\n+struct sdxi_cxt {\n+\tstruct sdxi_dev *sdxi;\n+\tunsigned int id;\n+\n+\t__le64 __iomem *db;\n+\n+\tstruct sdxi_cxt_ctl *cxt_ctl;\n+\tdma_addr_t cxt_ctl_dma;\n+\n+\tstruct sdxi_akey_table *akey_table;\n+\tdma_addr_t akey_table_dma;\n+\n+\tstruct sdxi_sq *sq;\n+};\n+\n+int sdxi_admin_cxt_init(struct sdxi_dev *sdxi);\n+\n+#endif /* DMA_SDXI_CONTEXT_H */\ndiff --git a/drivers/dma/sdxi/device.c b/drivers/dma/sdxi/device.c\nindex 80bd1bbd9c7c..636abc410dcd 100644\n--- a/drivers/dma/sdxi/device.c\n+++ b/drivers/dma/sdxi/device.c\n@@ -13,6 +13,7 @@\n #include \n #include \n \n+#include \"context.h\"\n #include \"hw.h\"\n #include \"mmio.h\"\n #include \"sdxi.h\"\n@@ -186,6 +187,16 @@ static int sdxi_fn_activate(struct sdxi_dev *sdxi)\n \t\t\t sdxi->L1_dma >> ilog2(SZ_4K));\n \tL2_ent->lv01_ptr = cpu_to_le64(lv01_ptr);\n \n+\t/*\n+\t * SDXI 1.0 4.1.8.4 Administrative Context\n+\t *\n+\t * The admin context will not consume descriptors until we\n+\t * write its doorbell later.\n+\t */\n+\terr = sdxi_admin_cxt_init(sdxi);\n+\tif (err)\n+\t\treturn err;\n+\n \treturn 0;\n }\n \ndiff --git a/drivers/dma/sdxi/hw.h b/drivers/dma/sdxi/hw.h\nindex 846c671c423f..b66eb22f7f90 100644\n--- a/drivers/dma/sdxi/hw.h\n+++ b/drivers/dma/sdxi/hw.h\n@@ -23,6 +23,7 @@\n \n #include \n #include \n+#include \n #include \n #include \n \n@@ -72,12 +73,39 @@ static_assert(sizeof(struct sdxi_cxt_ctl) == 64);\n /* SDXI 1.0 Table 3-5: Context Status (CXT_STS) */\n struct sdxi_cxt_sts {\n \t__u8 state;\n+#define SDXI_CXT_STS_STATE GENMASK(3, 0)\n \t__u8 misc0;\n \t__u8 rsvd_0[6];\n \t__le64 read_index;\n } __packed;\n static_assert(sizeof(struct sdxi_cxt_sts) == 16);\n \n+/* SDXI 1.0 Table 3-6: CXT_STS.state Encoding */\n+/* Valid values for FIELD_GET(SDXI_CXT_STS_STATE, sdxi_cxt_sts.state). */\n+enum cxt_sts_state {\n+\tCXTV_STOP_SW = 0x0,\n+\tCXTV_RUN = 0x1,\n+\tCXTV_STOPG_SW = 0x2,\n+\tCXTV_STOP_FN = 0x4,\n+\tCXTV_STOPG_FN = 0x6,\n+\tCXTV_ERR_FN = 0xf,\n+};\n+\n+/* SDXI 1.0 Table 3-7: AKey Table Entry (AKEY_ENT) */\n+struct sdxi_akey_ent {\n+\t__le16 intr_num;\n+#define SDXI_AKEY_ENT_VL BIT(0)\n+#define SDXI_AKEY_ENT_IV BIT(1)\n+#define SDXI_AKEY_ENT_INTR_NUM GENMASK(14, 4)\n+\t__le16 tgt_sfunc;\n+\t__le32 pasid;\n+\t__le16 stag;\n+\t__u8 rsvd_0[2];\n+\t__le16 rkey;\n+\t__u8 rsvd_1[2];\n+} __packed;\n+static_assert(sizeof(struct sdxi_akey_ent) == 16);\n+\n /* SDXI 1.0 Table 6-4: CST_BLK (Completion Status Block) */\n struct sdxi_cst_blk {\n \t__le64 signal;\n@@ -86,4 +114,19 @@ struct sdxi_cst_blk {\n } __packed;\n static_assert(sizeof(struct sdxi_cst_blk) == 32);\n \n+struct sdxi_desc {\n+\tunion {\n+\t\t/*\n+\t\t * SDXI 1.0 Table 6-3: DSC_GENERIC SDXI Descriptor\n+\t\t * Common Header and Footer Format\n+\t\t */\n+\t\tstruct_group_tagged(sdxi_dsc_generic, generic,\n+\t\t\t__le32 opcode;\n+\t\t\t__u8 operation[52];\n+\t\t\t__le64 csb_ptr;\n+\t\t);\n+\t};\n+} __packed;\n+static_assert(sizeof(struct sdxi_desc) == 64);\n+\n #endif /* DMA_SDXI_HW_H */\ndiff --git a/drivers/dma/sdxi/sdxi.h b/drivers/dma/sdxi/sdxi.h\nindex 6cda60bb33c4..4ef893ae15f3 100644\n--- a/drivers/dma/sdxi/sdxi.h\n+++ b/drivers/dma/sdxi/sdxi.h\n@@ -51,6 +51,8 @@ struct sdxi_dev {\n \tstruct dma_pool *cxt_ctl_pool;\n \tstruct dma_pool *cst_blk_pool;\n \n+\tstruct sdxi_cxt *admin_cxt;\n+\n \tconst struct sdxi_bus_ops *bus_ops;\n };\n \n","prefixes":["07/23"]}