{"id":2221942,"url":"http://patchwork.ozlabs.org/api/patches/2221942/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260410-sdxi-base-v1-5-1d184cb5c60a@amd.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260410-sdxi-base-v1-5-1d184cb5c60a@amd.com>","list_archive_url":null,"date":"2026-04-10T13:07:15","name":"[05/23] dmaengine: sdxi: Configure context tables","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"a839218a7903dea080632bde9336d13c679eb5b3","submitter":{"id":91626,"url":"http://patchwork.ozlabs.org/api/people/91626/?format=json","name":"Nathan Lynch via B4 Relay","email":"devnull+nathan.lynch.amd.com@kernel.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260410-sdxi-base-v1-5-1d184cb5c60a@amd.com/mbox/","series":[{"id":499458,"url":"http://patchwork.ozlabs.org/api/series/499458/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=499458","date":"2026-04-10T13:07:10","name":"dmaengine: Smart Data Accelerator Interface (SDXI) basic support","version":1,"mbox":"http://patchwork.ozlabs.org/series/499458/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2221942/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221942/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=F62tMkB3;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260410-sdxi-base-v1-5-1d184cb5c60a@amd.com>","References":"<20260410-sdxi-base-v1-0-1d184cb5c60a@amd.com>","In-Reply-To":"<20260410-sdxi-base-v1-0-1d184cb5c60a@amd.com>","To":"Vinod Koul ","Cc":"Wei Huang ,\n Mario Limonciello ,\n Bjorn Helgaas ,\n Jonathan Cameron ,\n Stephen Bates , PradeepVineshReddy.Kodamati@amd.com,\n John.Kariuki@amd.com, linux-pci@vger.kernel.org,\n linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,\n Nathan Lynch ","X-Mailer":"b4 0.15.2","X-Developer-Signature":"v=1; a=ed25519-sha256; t=1775826467; l=6822;\n i=nathan.lynch@amd.com; s=20260410; h=from:subject:message-id;\n bh=Zoq8VnkuwOO4eUQgVv+ADI1U5B7YsdpNi3XIpPjoUyQ=;\n b=eiX3CHjsjpXNYgDae34bwdmMk/1Im07HeB6UhGhBwp2oVcFBp7Bq1qAfPf8Iw8JSuHsIUWx9U\n JGP83swnWfODyMBgKKP3OmEDs3dFhka+uRvs6bWCWvrByBbzkxW+kL4","X-Developer-Key":"i=nathan.lynch@amd.com; a=ed25519;\n pk=PK4ozhq+/z9/2Jl5rgDmvHa9raVomv79qM8p1RAFpEw=","X-Endpoint-Received":"by B4 Relay for nathan.lynch@amd.com/20260410 with\n auth_id=728","X-Original-From":"Nathan Lynch ","Reply-To":"nathan.lynch@amd.com"},"content":"From: Nathan Lynch \n\nSDXI uses a two-level table hierarchy to track contexts. There is a\nsingle level 2 table per function which enumerates up to 512 level 1\ntables. Each level 1 table enumerates up to 128 contexts.\n\nAllocate and install the L2 table and a single L1 table, enough for\ncontext IDs 0-127 (i.e. the admin context with reserved id 0, plus 127\nclient contexts). For now, to avoid dynamic management of additional\nL1 tables, cap ctl2.max_cxt to 127.\n\nSince the table allocations are devres-managed, there is no\ncorresponding cleanup code required.\n\nCo-developed-by: Wei Huang \nSigned-off-by: Wei Huang \nSigned-off-by: Nathan Lynch \n---\n drivers/dma/sdxi/device.c | 40 +++++++++++++++++++++++++++++--\n drivers/dma/sdxi/hw.h | 61 +++++++++++++++++++++++++++++++++++++++++++++++\n drivers/dma/sdxi/mmio.h | 6 +++++\n drivers/dma/sdxi/sdxi.h | 5 ++++\n 4 files changed, 110 insertions(+), 2 deletions(-)","diff":"diff --git a/drivers/dma/sdxi/device.c b/drivers/dma/sdxi/device.c\nindex 1083fdddd72f..7e772ce81365 100644\n--- a/drivers/dma/sdxi/device.c\n+++ b/drivers/dma/sdxi/device.c\n@@ -8,8 +8,11 @@\n #include \n #include \n #include \n+#include \n+#include \n #include \n \n+#include \"hw.h\"\n #include \"mmio.h\"\n #include \"sdxi.h\"\n \n@@ -113,7 +116,8 @@ static int sdxi_dev_stop(struct sdxi_dev *sdxi)\n */\n static int sdxi_fn_activate(struct sdxi_dev *sdxi)\n {\n-\tu64 version, cap0, cap1, ctl2;\n+\tu64 version, cap0, cap1, ctl2, cxt_l2, lv01_ptr;\n+\tstruct sdxi_cxt_L2_ent *L2_ent;\n \tint err;\n \n \t/*\n@@ -137,7 +141,13 @@ static int sdxi_fn_activate(struct sdxi_dev *sdxi)\n \n \tcap1 = sdxi_read64(sdxi, SDXI_MMIO_CAP1);\n \tsdxi->op_grp_cap = FIELD_GET(SDXI_MMIO_CAP1_OPB_000_CAP, cap1);\n-\tsdxi->max_cxtid = FIELD_GET(SDXI_MMIO_CAP1_MAX_CXT, cap1);\n+\n+\t/*\n+\t * Constrain the number of client contexts supported by the\n+\t * driver to what fits in a single L1 table.\n+\t */\n+\tsdxi->max_cxtid = min(SDXI_L1_TABLE_ENTRIES - 1,\n+\t\t\t FIELD_GET(SDXI_MMIO_CAP1_MAX_CXT, cap1));\n \n \t/* Apply our configuration. */\n \tctl2 = FIELD_PREP(SDXI_MMIO_CTL2_MAX_CXT, sdxi->max_cxtid);\n@@ -149,6 +159,32 @@ static int sdxi_fn_activate(struct sdxi_dev *sdxi)\n \t\t\t FIELD_GET(SDXI_MMIO_CAP1_OPB_000_CAP, cap1));\n \tsdxi_write64(sdxi, SDXI_MMIO_CTL2, ctl2);\n \n+\t/* SDXI 1.0 4.1.8.2 Context Level 2 Table Setup */\n+\tsdxi->L2_table = dmam_alloc_coherent(sdxi_to_dev(sdxi),\n+\t\t\t\t\t sizeof(*sdxi->L2_table),\n+\t\t\t\t\t &sdxi->L2_dma, GFP_KERNEL);\n+\tif (!sdxi->L2_table)\n+\t\treturn -ENOMEM;\n+\n+\tcxt_l2 = FIELD_PREP(SDXI_MMIO_CXT_L2_PTR, sdxi->L2_dma >> ilog2(SZ_4K));\n+\tsdxi_write64(sdxi, SDXI_MMIO_CXT_L2, cxt_l2);\n+\n+\t/* SDXI 1.0 4.1.8.3 Context Level 1 Table Setup */\n+\tsdxi->L1_table = dmam_alloc_coherent(sdxi_to_dev(sdxi),\n+\t\t\t\t\t sizeof(*sdxi->L1_table),\n+\t\t\t\t\t &sdxi->L1_dma, GFP_KERNEL);\n+\tif (!sdxi->L1_table)\n+\t\treturn -ENOMEM;\n+\t/*\n+\t * SDXI 1.0 4.1.8.3.c: Initialize the Context level 2 table to\n+\t * point to the Context Level 1 [table].\n+\t */\n+\tL2_ent = &sdxi->L2_table->entry[0];\n+\tlv01_ptr = FIELD_PREP(SDXI_CXT_L2_ENT_VL, 1);\n+\tlv01_ptr |= FIELD_PREP(SDXI_CXT_L2_ENT_LV01_PTR,\n+\t\t\t sdxi->L1_dma >> ilog2(SZ_4K));\n+\tL2_ent->lv01_ptr = cpu_to_le64(lv01_ptr);\n+\n \treturn 0;\n }\n \ndiff --git a/drivers/dma/sdxi/hw.h b/drivers/dma/sdxi/hw.h\nnew file mode 100644\nindex 000000000000..df520ca7792b\n--- /dev/null\n+++ b/drivers/dma/sdxi/hw.h\n@@ -0,0 +1,61 @@\n+/* SPDX-License-Identifier: GPL-2.0-only */\n+/* Copyright Advanced Micro Devices, Inc. */\n+\n+/*\n+ * Control structures and constants defined in the SDXI specification,\n+ * with low-level accessors. The ordering of the structures here\n+ * follows the order of their definitions in the SDXI spec.\n+ *\n+ * Names of structures, members, and subfields (bit ranges within\n+ * members) are written to match the spec, generally. E.g. struct\n+ * sdxi_cxt_L2_ent corresponds to CXT_L2_ENT in the spec.\n+ *\n+ * Note: a member can have a subfield whose name is identical to the\n+ * member's name. E.g. CXT_L2_ENT's lv01_ptr.\n+ *\n+ * All reserved fields and bits (usually named \"rsvd\" or some\n+ * variation) must be set to zero by the driver unless otherwise\n+ * specified.\n+ */\n+\n+#ifndef DMA_SDXI_HW_H\n+#define DMA_SDXI_HW_H\n+\n+#include \n+#include \n+#include \n+#include \n+\n+/* SDXI 1.0 Table 3-2: Context Level 2 Table Entry (CXT_L2_ENT) */\n+struct sdxi_cxt_L2_ent {\n+\t__le64 lv01_ptr;\n+#define SDXI_CXT_L2_ENT_VL BIT_ULL(0)\n+#define SDXI_CXT_L2_ENT_LV01_PTR GENMASK_ULL(63, 12)\n+} __packed;\n+static_assert(sizeof(struct sdxi_cxt_L2_ent) == 8);\n+\n+/* SDXI 1.0 3.2.1 Context Level 2 Table */\n+#define SDXI_L2_TABLE_ENTRIES 512\n+struct sdxi_cxt_L2_table {\n+\tstruct sdxi_cxt_L2_ent entry[SDXI_L2_TABLE_ENTRIES];\n+};\n+static_assert(sizeof(struct sdxi_cxt_L2_table) == 4096);\n+\n+/* SDXI 1.0 Table 3-3: Context Level 1 Table Entry (CXT_L1_ENT) */\n+struct sdxi_cxt_L1_ent {\n+\t__le64 cxt_ctl_ptr;\n+\t__le64 akey_ptr;\n+\t__le32 misc0;\n+\t__le32 opb_000_enb;\n+\t__u8 rsvd_0[8];\n+} __packed;\n+static_assert(sizeof(struct sdxi_cxt_L1_ent) == 32);\n+\n+/* SDXI 1.0 3.2.2 Context Level 1 Table */\n+#define SDXI_L1_TABLE_ENTRIES 128\n+struct sdxi_cxt_L1_table {\n+\tstruct sdxi_cxt_L1_ent entry[SDXI_L1_TABLE_ENTRIES];\n+};\n+static_assert(sizeof(struct sdxi_cxt_L1_table) == 4096);\n+\n+#endif /* DMA_SDXI_HW_H */\ndiff --git a/drivers/dma/sdxi/mmio.h b/drivers/dma/sdxi/mmio.h\nindex c9a11c3f2f76..d8d631849938 100644\n--- a/drivers/dma/sdxi/mmio.h\n+++ b/drivers/dma/sdxi/mmio.h\n@@ -19,6 +19,9 @@ enum sdxi_reg {\n \tSDXI_MMIO_CAP0 = 0x00200,\n \tSDXI_MMIO_CAP1 = 0x00208,\n \tSDXI_MMIO_VERSION = 0x00210,\n+\n+\t/* SDXI 1.0 9.2 Context and RKey Table Registers */\n+\tSDXI_MMIO_CXT_L2 = 0x10000,\n };\n \n /* SDXI 1.0 Table 9-2: MMIO_CTL0 */\n@@ -48,4 +51,7 @@ enum sdxi_reg {\n #define SDXI_MMIO_VERSION_MINOR GENMASK_ULL(7, 0)\n #define SDXI_MMIO_VERSION_MAJOR GENMASK_ULL(23, 16)\n \n+/* SDXI 1.0 Table 9-9: MMIO_CXT_L2 */\n+#define SDXI_MMIO_CXT_L2_PTR GENMASK_ULL(63, 12)\n+\n #endif /* DMA_SDXI_MMIO_H */\ndiff --git a/drivers/dma/sdxi/sdxi.h b/drivers/dma/sdxi/sdxi.h\nindex 427118e60aa6..185f58b725da 100644\n--- a/drivers/dma/sdxi/sdxi.h\n+++ b/drivers/dma/sdxi/sdxi.h\n@@ -41,6 +41,11 @@ struct sdxi_dev {\n \tu16 max_cxtid;\t\t\t/* Maximum context ID allowed. */\n \tu32 op_grp_cap;\t\t\t/* supported operation group cap */\n \n+\tstruct sdxi_cxt_L2_table *L2_table;\n+\tdma_addr_t L2_dma;\n+\tstruct sdxi_cxt_L1_table *L1_table;\n+\tdma_addr_t L1_dma;\n+\n \tconst struct sdxi_bus_ops *bus_ops;\n };\n \n","prefixes":["05/23"]}