{"id":2221928,"url":"http://patchwork.ozlabs.org/api/patches/2221928/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260410-sdxi-base-v1-4-1d184cb5c60a@amd.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260410-sdxi-base-v1-4-1d184cb5c60a@amd.com>","list_archive_url":null,"date":"2026-04-10T13:07:14","name":"[04/23] dmaengine: sdxi: Feature discovery and initial configuration","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"c2e163d894384ac0020d0f80299135683746eebb","submitter":{"id":91626,"url":"http://patchwork.ozlabs.org/api/people/91626/?format=json","name":"Nathan Lynch via B4 Relay","email":"devnull+nathan.lynch.amd.com@kernel.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260410-sdxi-base-v1-4-1d184cb5c60a@amd.com/mbox/","series":[{"id":499458,"url":"http://patchwork.ozlabs.org/api/series/499458/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=499458","date":"2026-04-10T13:07:10","name":"dmaengine: Smart Data Accelerator Interface (SDXI) basic support","version":1,"mbox":"http://patchwork.ozlabs.org/series/499458/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2221928/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221928/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=clrbc0Kv;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260410-sdxi-base-v1-4-1d184cb5c60a@amd.com>","References":"<20260410-sdxi-base-v1-0-1d184cb5c60a@amd.com>","In-Reply-To":"<20260410-sdxi-base-v1-0-1d184cb5c60a@amd.com>","To":"Vinod Koul ","Cc":"Wei Huang ,\n Mario Limonciello ,\n Bjorn Helgaas ,\n Jonathan Cameron ,\n Stephen Bates , PradeepVineshReddy.Kodamati@amd.com,\n John.Kariuki@amd.com, linux-pci@vger.kernel.org,\n linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,\n Nathan Lynch ","X-Mailer":"b4 0.15.2","X-Developer-Signature":"v=1; a=ed25519-sha256; t=1775826467; l=9474;\n i=nathan.lynch@amd.com; s=20260410; h=from:subject:message-id;\n bh=b7xu936IWaAWui2gDis8KlNNC8TGpATPQfcAYDAr6kM=;\n b=y69NHSxZh8DFXKYmeqC9Zq2QsmbA5eS5d6E5M/G8yii7wjB+0qj+1Z4ui552Kxyv9f01qwFqO\n ndycO+cNlbgC8bDMFQzRcOr2GONhO6O2ZxFr5wCAQ0uVJ0jMyUN5cQM","X-Developer-Key":"i=nathan.lynch@amd.com; a=ed25519;\n pk=PK4ozhq+/z9/2Jl5rgDmvHa9raVomv79qM8p1RAFpEw=","X-Endpoint-Received":"by B4 Relay for nathan.lynch@amd.com/20260410 with\n auth_id=728","X-Original-From":"Nathan Lynch ","Reply-To":"nathan.lynch@amd.com"},"content":"From: Nathan Lynch \n\nAfter bus-specific initialization, force the SDXI function to stopped\nstate. This is the expected state from reset, but kexec or driver bugs\ncan leave a function in other states from which the initialization\ncode must be able to recover.\n\nDiscover via the capability registers the doorbell region stride, the\nmaximum supported context ID, the operation groups implemented, and\nlimits on buffer and control structure sizes. The driver has the\noption of writing more conservative limits to the ctl2 register, but\nit uses those supplied by the implementation for now.\n\nIntroduce device register definitions and associated masks via mmio.h.\n\nAdd convenience wrappers which are first used here:\n- sdxi_dbg()\n- sdxi_info()\n- sdxi_err()\n- sdxi_read64()\n- sdxi_write64()\n\nReport the version of the standard to which the device conforms, e.g.\n\n sdxi 0000:00:03.0: SDXI 1.0 device found\n\nCo-developed-by: Wei Huang \nSigned-off-by: Wei Huang \nSigned-off-by: Nathan Lynch \n---\n drivers/dma/sdxi/device.c | 149 +++++++++++++++++++++++++++++++++++++++++++++-\n drivers/dma/sdxi/mmio.h | 51 ++++++++++++++++\n drivers/dma/sdxi/sdxi.h | 23 +++++++\n 3 files changed, 222 insertions(+), 1 deletion(-)","diff":"diff --git a/drivers/dma/sdxi/device.c b/drivers/dma/sdxi/device.c\nindex b718ce04afa0..1083fdddd72f 100644\n--- a/drivers/dma/sdxi/device.c\n+++ b/drivers/dma/sdxi/device.c\n@@ -5,14 +5,157 @@\n * Copyright Advanced Micro Devices, Inc.\n */\n \n+#include \n+#include \n #include \n #include \n \n+#include \"mmio.h\"\n #include \"sdxi.h\"\n \n+enum sdxi_fn_gsv {\n+\tSDXI_GSV_STOP,\n+\tSDXI_GSV_INIT,\n+\tSDXI_GSV_ACTIVE,\n+\tSDXI_GSV_STOPG_SF,\n+\tSDXI_GSV_STOPG_HD,\n+\tSDXI_GSV_ERROR,\n+};\n+\n+static const char *const gsv_strings[] = {\n+\t[SDXI_GSV_STOP] = \"stopped\",\n+\t[SDXI_GSV_INIT] = \"initializing\",\n+\t[SDXI_GSV_ACTIVE] = \"active\",\n+\t[SDXI_GSV_STOPG_SF] = \"soft stopping\",\n+\t[SDXI_GSV_STOPG_HD] = \"hard stopping\",\n+\t[SDXI_GSV_ERROR] = \"error\",\n+};\n+\n+static const char *gsv_str(enum sdxi_fn_gsv gsv)\n+{\n+\tif ((size_t)gsv < ARRAY_SIZE(gsv_strings))\n+\t\treturn gsv_strings[(size_t)gsv];\n+\n+\tWARN_ONCE(1, \"unexpected gsv %u\\n\", gsv);\n+\n+\treturn \"unknown\";\n+}\n+\n+enum sdxi_fn_gsr {\n+\tSDXI_GSRV_RESET,\n+\tSDXI_GSRV_STOP_SF,\n+\tSDXI_GSRV_STOP_HD,\n+\tSDXI_GSRV_ACTIVE,\n+};\n+\n+static enum sdxi_fn_gsv sdxi_dev_gsv(const struct sdxi_dev *sdxi)\n+{\n+\treturn (enum sdxi_fn_gsv)FIELD_GET(SDXI_MMIO_STS0_FN_GSV,\n+\t\t\t\t\t sdxi_read64(sdxi, SDXI_MMIO_STS0));\n+}\n+\n+static void sdxi_write_fn_gsr(struct sdxi_dev *sdxi, enum sdxi_fn_gsr cmd)\n+{\n+\tu64 ctl0 = sdxi_read64(sdxi, SDXI_MMIO_CTL0);\n+\n+\tFIELD_MODIFY(SDXI_MMIO_CTL0_FN_GSR, &ctl0, cmd);\n+\tsdxi_write64(sdxi, SDXI_MMIO_CTL0, ctl0);\n+}\n+\n+/* Get the device to the GSV_STOP state. */\n+static int sdxi_dev_stop(struct sdxi_dev *sdxi)\n+{\n+\tunsigned long deadline = jiffies + msecs_to_jiffies(1000);\n+\tbool reset_issued = false;\n+\n+\tdo {\n+\t\tenum sdxi_fn_gsv status = sdxi_dev_gsv(sdxi);\n+\n+\t\tsdxi_dbg(sdxi, \"%s: function state: %s\\n\", __func__, gsv_str(status));\n+\n+\t\tswitch (status) {\n+\t\tcase SDXI_GSV_ACTIVE:\n+\t\t\tsdxi_write_fn_gsr(sdxi, SDXI_GSRV_STOP_SF);\n+\t\t\tbreak;\n+\t\tcase SDXI_GSV_ERROR:\n+\t\t\tif (!reset_issued) {\n+\t\t\t\tsdxi_info(sdxi,\n+\t\t\t\t\t \"function in error state, issuing reset\\n\");\n+\t\t\t\tsdxi_write_fn_gsr(sdxi, SDXI_GSRV_RESET);\n+\t\t\t\treset_issued = true;\n+\t\t\t} else {\n+\t\t\t\tfsleep(1000);\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tcase SDXI_GSV_STOP:\n+\t\t\treturn 0;\n+\t\tcase SDXI_GSV_INIT:\n+\t\tcase SDXI_GSV_STOPG_SF:\n+\t\tcase SDXI_GSV_STOPG_HD:\n+\t\t\t/* transitional states, wait */\n+\t\t\tsdxi_dbg(sdxi, \"waiting for stop (gsv = %u)\\n\",\n+\t\t\t\t status);\n+\t\t\tfsleep(1000);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tsdxi_err(sdxi, \"unknown gsv %u, giving up\\n\", status);\n+\t\t\treturn -EIO;\n+\t\t}\n+\t} while (time_before(jiffies, deadline));\n+\n+\tsdxi_err(sdxi, \"stop attempt timed out, current status %u\\n\",\n+\t\tsdxi_dev_gsv(sdxi));\n+\treturn -ETIMEDOUT;\n+}\n+\n+/*\n+ * See SDXI 1.0 4.1.8 Activation of the SDXI Function by Software.\n+ */\n+static int sdxi_fn_activate(struct sdxi_dev *sdxi)\n+{\n+\tu64 version, cap0, cap1, ctl2;\n+\tint err;\n+\n+\t/*\n+\t * Clear any existing configuration from MMIO_CTL0 and ensure\n+\t * the function is in GSV_STOP state.\n+\t */\n+\tsdxi_write64(sdxi, SDXI_MMIO_CTL0, 0);\n+\terr = sdxi_dev_stop(sdxi);\n+\tif (err)\n+\t\treturn err;\n+\n+\tversion = sdxi_read64(sdxi, SDXI_MMIO_VERSION);\n+\tsdxi_info(sdxi, \"SDXI %llu.%llu device found\\n\",\n+\t\t FIELD_GET(SDXI_MMIO_VERSION_MAJOR, version),\n+\t\t FIELD_GET(SDXI_MMIO_VERSION_MINOR, version));\n+\n+\t/* Read capabilities and features. */\n+\tcap0 = sdxi_read64(sdxi, SDXI_MMIO_CAP0);\n+\tsdxi->db_stride = SZ_4K;\n+\tsdxi->db_stride *= 1U << FIELD_GET(SDXI_MMIO_CAP0_DB_STRIDE, cap0);\n+\n+\tcap1 = sdxi_read64(sdxi, SDXI_MMIO_CAP1);\n+\tsdxi->op_grp_cap = FIELD_GET(SDXI_MMIO_CAP1_OPB_000_CAP, cap1);\n+\tsdxi->max_cxtid = FIELD_GET(SDXI_MMIO_CAP1_MAX_CXT, cap1);\n+\n+\t/* Apply our configuration. */\n+\tctl2 = FIELD_PREP(SDXI_MMIO_CTL2_MAX_CXT, sdxi->max_cxtid);\n+\tctl2 |= FIELD_PREP(SDXI_MMIO_CTL2_MAX_BUFFER,\n+\t\t\t FIELD_GET(SDXI_MMIO_CAP1_MAX_BUFFER, cap1));\n+\tctl2 |= FIELD_PREP(SDXI_MMIO_CTL2_MAX_AKEY_SZ,\n+\t\t\t FIELD_GET(SDXI_MMIO_CAP1_MAX_AKEY_SZ, cap1));\n+\tctl2 |= FIELD_PREP(SDXI_MMIO_CTL2_OPB_000_AVL,\n+\t\t\t FIELD_GET(SDXI_MMIO_CAP1_OPB_000_CAP, cap1));\n+\tsdxi_write64(sdxi, SDXI_MMIO_CTL2, ctl2);\n+\n+\treturn 0;\n+}\n+\n int sdxi_register(struct device *dev, const struct sdxi_bus_ops *ops)\n {\n \tstruct sdxi_dev *sdxi;\n+\tint err;\n \n \tsdxi = devm_kzalloc(dev, sizeof(*sdxi), GFP_KERNEL);\n \tif (!sdxi)\n@@ -22,5 +165,9 @@ int sdxi_register(struct device *dev, const struct sdxi_bus_ops *ops)\n \tsdxi->bus_ops = ops;\n \tdev_set_drvdata(dev, sdxi);\n \n-\treturn sdxi->bus_ops->init(sdxi);\n+\terr = sdxi->bus_ops->init(sdxi);\n+\tif (err)\n+\t\treturn err;\n+\n+\treturn sdxi_fn_activate(sdxi);\n }\ndiff --git a/drivers/dma/sdxi/mmio.h b/drivers/dma/sdxi/mmio.h\nnew file mode 100644\nindex 000000000000..c9a11c3f2f76\n--- /dev/null\n+++ b/drivers/dma/sdxi/mmio.h\n@@ -0,0 +1,51 @@\n+/* SPDX-License-Identifier: GPL-2.0-only */\n+\n+/*\n+ * SDXI MMIO register offsets and layouts.\n+ *\n+ * Copyright Advanced Micro Devices, Inc.\n+ */\n+\n+#ifndef DMA_SDXI_MMIO_H\n+#define DMA_SDXI_MMIO_H\n+\n+#include \n+\n+enum sdxi_reg {\n+\t/* SDXI 1.0 9.1 General Control and Status Registers */\n+\tSDXI_MMIO_CTL0 = 0x00000,\n+\tSDXI_MMIO_CTL2 = 0x00010,\n+\tSDXI_MMIO_STS0 = 0x00100,\n+\tSDXI_MMIO_CAP0 = 0x00200,\n+\tSDXI_MMIO_CAP1 = 0x00208,\n+\tSDXI_MMIO_VERSION = 0x00210,\n+};\n+\n+/* SDXI 1.0 Table 9-2: MMIO_CTL0 */\n+#define SDXI_MMIO_CTL0_FN_GSR GENMASK_ULL(1, 0)\n+\n+/* SDXI 1.0 Table 9-4: MMIO_CTL2 */\n+#define SDXI_MMIO_CTL2_MAX_BUFFER GENMASK_ULL(3, 0)\n+#define SDXI_MMIO_CTL2_MAX_AKEY_SZ GENMASK_ULL(15, 12)\n+#define SDXI_MMIO_CTL2_MAX_CXT GENMASK_ULL(31, 16)\n+#define SDXI_MMIO_CTL2_OPB_000_AVL GENMASK_ULL(63, 32)\n+\n+/* SDXI 1.0 Table 9-5: MMIO_STS0 */\n+#define SDXI_MMIO_STS0_FN_GSV GENMASK_ULL(2, 0)\n+\n+/* SDXI 1.0 Table 9-6: MMIO_CAP0 */\n+#define SDXI_MMIO_CAP0_SFUNC GENMASK_ULL(15, 0)\n+#define SDXI_MMIO_CAP0_DB_STRIDE GENMASK_ULL(22, 20)\n+#define SDXI_MMIO_CAP0_MAX_DS_RING_SZ GENMASK_ULL(28, 24)\n+\n+/* SDXI 1.0 Table 9-7: MMIO_CAP1 */\n+#define SDXI_MMIO_CAP1_MAX_BUFFER GENMASK_ULL(3, 0)\n+#define SDXI_MMIO_CAP1_MAX_AKEY_SZ GENMASK_ULL(15, 12)\n+#define SDXI_MMIO_CAP1_MAX_CXT GENMASK_ULL(31, 16)\n+#define SDXI_MMIO_CAP1_OPB_000_CAP GENMASK_ULL(63, 32)\n+\n+/* SDXI 1.0 Table 9-8: MMIO_VERSION */\n+#define SDXI_MMIO_VERSION_MINOR GENMASK_ULL(7, 0)\n+#define SDXI_MMIO_VERSION_MAJOR GENMASK_ULL(23, 16)\n+\n+#endif /* DMA_SDXI_MMIO_H */\ndiff --git a/drivers/dma/sdxi/sdxi.h b/drivers/dma/sdxi/sdxi.h\nindex 9430f3b8d0b3..427118e60aa6 100644\n--- a/drivers/dma/sdxi/sdxi.h\n+++ b/drivers/dma/sdxi/sdxi.h\n@@ -9,8 +9,12 @@\n #define DMA_SDXI_H\n \n #include \n+#include \n+#include \n #include \n \n+#include \"mmio.h\"\n+\n #define SDXI_DRV_DESC\t\t\"SDXI driver\"\n \n struct sdxi_dev;\n@@ -32,6 +36,11 @@ struct sdxi_dev {\n \tvoid __iomem *ctrl_regs;\t/* virt addr of ctrl registers */\n \tvoid __iomem *dbs;\t\t/* virt addr of doorbells */\n \n+\t/* hardware capabilities (from cap0 & cap1) */\n+\tu32 db_stride;\t\t\t/* doorbell stride in bytes */\n+\tu16 max_cxtid;\t\t\t/* Maximum context ID allowed. */\n+\tu32 op_grp_cap;\t\t\t/* supported operation group cap */\n+\n \tconst struct sdxi_bus_ops *bus_ops;\n };\n \n@@ -40,6 +49,20 @@ static inline struct device *sdxi_to_dev(const struct sdxi_dev *sdxi)\n \treturn sdxi->dev;\n }\n \n+#define sdxi_dbg(s, fmt, ...) dev_dbg(sdxi_to_dev(s), fmt, ## __VA_ARGS__)\n+#define sdxi_info(s, fmt, ...) dev_info(sdxi_to_dev(s), fmt, ## __VA_ARGS__)\n+#define sdxi_err(s, fmt, ...) dev_err(sdxi_to_dev(s), fmt, ## __VA_ARGS__)\n+\n int sdxi_register(struct device *dev, const struct sdxi_bus_ops *ops);\n \n+static inline u64 sdxi_read64(const struct sdxi_dev *sdxi, enum sdxi_reg reg)\n+{\n+\treturn ioread64(sdxi->ctrl_regs + reg);\n+}\n+\n+static inline void sdxi_write64(struct sdxi_dev *sdxi, enum sdxi_reg reg, u64 val)\n+{\n+\tiowrite64(val, sdxi->ctrl_regs + reg);\n+}\n+\n #endif /* DMA_SDXI_H */\n","prefixes":["04/23"]}