{"id":2221650,"url":"http://patchwork.ozlabs.org/api/patches/2221650/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260410033723.1225983-1-gaosong@loongson.cn/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260410033723.1225983-1-gaosong@loongson.cn>","list_archive_url":null,"date":"2026-04-10T03:37:23","name":"[v2] target/loongarch: Add support for dbar hint variants","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"cb87d65c974ec4d5b87155d185add89e7c1848b9","submitter":{"id":82024,"url":"http://patchwork.ozlabs.org/api/people/82024/?format=json","name":"gaosong","email":"gaosong@loongson.cn"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260410033723.1225983-1-gaosong@loongson.cn/mbox/","series":[{"id":499386,"url":"http://patchwork.ozlabs.org/api/series/499386/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499386","date":"2026-04-10T03:37:23","name":"[v2] target/loongarch: Add support for dbar hint variants","version":2,"mbox":"http://patchwork.ozlabs.org/series/499386/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2221650/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221650/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":"legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)","Received":["from lists.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fsNT50qdlz1yGb\n\tfor ; Fri, 10 Apr 2026 14:03:37 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wB35S-00013i-FX; Fri, 10 Apr 2026 00:03:19 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wB35N-00013a-CI\n for qemu-devel@nongnu.org; Fri, 10 Apr 2026 00:03:13 -0400","from mail.loongson.cn ([114.242.206.163])\n by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from ) id 1wB35K-0004kP-46\n for qemu-devel@nongnu.org; Fri, 10 Apr 2026 00:03:13 -0400","from loongson.cn (unknown [10.2.5.185])\n by gateway (Coremail) with SMTP id _____8Dx98F3dthp990jAA--.1073S3;\n Fri, 10 Apr 2026 12:03:03 +0800 (CST)","from localhost.localdomain (unknown [10.2.5.185])\n by front1 (Coremail) with SMTP id qMiowJCxPMJ0dthpWhdqAA--.3585S2;\n Fri, 10 Apr 2026 12:03:01 +0800 (CST)"],"From":"Song Gao ","To":"maobibo@loongson.cn","Cc":"qemu-devel@nongnu.org, philmd@linaro.org, richard.henderson@linaro.org,\n lixianglai@loongson.cn, yijun@loongson.cn, chenhuacai@loongson.cn","Subject":"[PATCH v2] target/loongarch: Add support for dbar hint variants","Date":"Fri, 10 Apr 2026 11:37:23 +0800","Message-Id":"<20260410033723.1225983-1-gaosong@loongson.cn>","X-Mailer":"git-send-email 2.39.1","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-CM-TRANSID":"qMiowJCxPMJ0dthpWhdqAA--.3585S2","X-CM-SenderInfo":"5jdr20tqj6z05rqj20fqof0/","X-Coremail-Antispam":"1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7\n ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx\n nUUI43ZEXa7xR_UUUUUUUUU==","Received-SPF":"pass client-ip=114.242.206.163;\n envelope-from=gaosong@loongson.cn;\n helo=mail.loongson.cn","X-Spam_score_int":"-18","X-Spam_score":"-1.9","X-Spam_bar":"-","X-Spam_report":"(-1.9 / 5.0 requ) BAYES_00=-1.9,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"LoongArch architecture (since LA664) introduces fine-grained dbar\nhints that allow controlling which memory accesses are ordered by\nthe barrier. Previously, all dbar instructions were treated as a\nfull barrier (TCG_MO_ALL | TCG_BAR_SC).\n\nThis patch adds support for decoding dbar hints and emitting the\nappropriate TCG memory barrier flags. For CPUs that do not advertise\nthe DBAR_HINTS feature (cpucfg3.DBAR_HINTS = 0), all dbar hints\nfall back to a full barrier, preserving compatibility.\n\nThe hint encoding follows the LoongArch v1.10 specification:\n * Bit3: barrier for previous read (0: true, 1: false)\n * Bit2: barrier for previous write (0: true, 1: false)\n * Bit1: barrier for succeeding read (0: true, 1: false)\n * Bit0: barrier for succeeding write (0: true, 1: false)\n\nThe mapping to TCG memory order flags is as follows:\n TCG_BAR_SC |TCG_MO_LD_LD | TCG_MO_LD_ST;\n TCG_BAR_SC |TCG_MO_ST_LD | TCG_MO_ST_ST;\n TCG_BAR_SC |TCG_MO_LD_LD | TCG_MO_ST_LD;\n TCG_BAR_SC |TCG_MO_ST_ST | TCG_MO_LD_ST;\n\nSpecial hint handling:\n- hint 0x700: LL/SC loop barrier, treated as a full barrier as recommended.\n- hint 0xf and 0x1f: reserved/no-op, treated as no operation\n\nSigned-off-by: Song Gao \n---\n target/loongarch/cpu.c | 4 ++\n .../tcg/insn_trans/trans_memory.c.inc | 62 ++++++++++++++++++-\n target/loongarch/tcg/translate.c | 1 +\n target/loongarch/translate.h | 3 +\n 4 files changed, 68 insertions(+), 2 deletions(-)","diff":"diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c\nindex e22568c84a..d8d106b07e 100644\n--- a/target/loongarch/cpu.c\n+++ b/target/loongarch/cpu.c\n@@ -455,6 +455,10 @@ static void loongarch_max_initfn(Object *obj)\n data = FIELD_DP32(data, CPUCFG2, LLACQ_SCREL, 1);\n data = FIELD_DP32(data, CPUCFG2, SCQ, 1);\n cpu->env.cpucfg[2] = data;\n+\n+ data = cpu->env.cpucfg[3];\n+ data = FIELD_DP32(data, CPUCFG3, DBAR_HINTS, 1);\n+ cpu->env.cpucfg[3] = data;\n }\n }\n \ndiff --git a/target/loongarch/tcg/insn_trans/trans_memory.c.inc b/target/loongarch/tcg/insn_trans/trans_memory.c.inc\nindex e287d46363..e1146fe9ec 100644\n--- a/target/loongarch/tcg/insn_trans/trans_memory.c.inc\n+++ b/target/loongarch/tcg/insn_trans/trans_memory.c.inc\n@@ -137,11 +137,69 @@ static bool trans_preldx(DisasContext *ctx, arg_preldx * a)\n return true;\n }\n \n+/*\n+ * Decode dbar hint and emit appropriate TCG memory barrier.\n+ *\n+ * The hint is a 5-bit field (0-31) encoded in the instruction.\n+ * For hint 0x700 (special LL/SC loop barrier), treat as full barrier.\n+ *\n+ * See LoongArch Reference Manual v1.10, Section 4.2.2 for details.\n+ */\n static bool trans_dbar(DisasContext *ctx, arg_dbar * a)\n {\n- tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);\n+ int hint = a->imm;\n+ TCGBar bar_flags = 0;\n+\n+ /* Reserved/no-op hints: 0xf and 0x1f */\n+ if (hint == 0xf || hint == 0x1f) {\n+ return true;\n+ }\n+\n+ /* If the CPU does not support fine-grained hints,or for the special LL/SC\n+ * loop barrier (0x700), emit a full barrier.\n+ */\n+ if (!avail_DBAR_HINT(ctx) || hint == 0x700) {\n+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);\n+ return true;\n+ }\n+\n+ /*\n+ * Fine-grained hint decoding:\n+ * Bits 3-0 control which accesses must be ordered.\n+ * Bit3: barrier for previous read (0: true, 1: false)\n+ * Bit2: barrier for previous write (0: true, 1: false)\n+ * Bit1: barrier for succeeding read (0: true, 1: false)\n+ * Bit0: barrier for succeeding write (0: true, 1: false)\n+ *\n+ * For each combination, we set the corresponding TCG_MO_* flag if both\n+ * sides of the barrier require ordering.\n+ */\n+\n+ bool prev_rd = !(hint & 0x08); /* bit3 */\n+ bool prev_wr = !(hint & 0x04); /* bit2 */\n+ bool succ_rd = !(hint & 0x02); /* bit1 */\n+ bool succ_wr = !(hint & 0x01); /* bit0 */\n+\n+ if (prev_rd) {\n+ bar_flags |= TCG_MO_LD_LD | TCG_MO_LD_ST;\n+ }\n+ if (prev_wr) {\n+ bar_flags |= TCG_MO_ST_LD | TCG_MO_ST_ST;\n+ }\n+ if (succ_rd) {\n+ bar_flags |= TCG_MO_LD_LD | TCG_MO_ST_LD;\n+ }\n+ if (succ_wr) {\n+ bar_flags |= TCG_MO_ST_ST | TCG_MO_LD_ST;\n+ }\n+\n+ if (bar_flags == 0) {\n+ bar_flags = TCG_MO_ALL;\n+ }\n+\n+ tcg_gen_mb(bar_flags | TCG_BAR_SC);\n return true;\n-}\n+ }\n \n static bool trans_ibar(DisasContext *ctx, arg_ibar *a)\n {\ndiff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c\nindex b9ed13d19c..49280b1dd3 100644\n--- a/target/loongarch/tcg/translate.c\n+++ b/target/loongarch/tcg/translate.c\n@@ -149,6 +149,7 @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase,\n \n ctx->cpucfg1 = env->cpucfg[1];\n ctx->cpucfg2 = env->cpucfg[2];\n+ ctx->cpucfg3 = env->cpucfg[3];\n }\n \n static void loongarch_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)\ndiff --git a/target/loongarch/translate.h b/target/loongarch/translate.h\nindex ba1c89e57b..8aa8325dc6 100644\n--- a/target/loongarch/translate.h\n+++ b/target/loongarch/translate.h\n@@ -43,6 +43,8 @@\n #define avail_LLACQ_SCREL(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LLACQ_SCREL))\n #define avail_LLACQ_SCREL_64(C) (avail_64(C) && avail_LLACQ_SCREL(C))\n \n+#define avail_DBAR_HINT(C) (FIELD_EX32((C)->cpucfg3, CPUCFG3, DBAR_HINTS))\n+\n /*\n * If an operation is being performed on less than TARGET_LONG_BITS,\n * it may require the inputs to be sign- or zero-extended; which will\n@@ -66,6 +68,7 @@ typedef struct DisasContext {\n bool va32; /* 32-bit virtual address */\n uint32_t cpucfg1;\n uint32_t cpucfg2;\n+ uint32_t cpucfg3;\n } DisasContext;\n \n void generate_exception(DisasContext *ctx, int excp);\n","prefixes":["v2"]}