{"id":2220206,"url":"http://patchwork.ozlabs.org/api/patches/2220206/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260406154935.144674-4-djordje.todorovic@htecgroup.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260406154935.144674-4-djordje.todorovic@htecgroup.com>","list_archive_url":null,"date":"2026-04-06T15:49:41","name":"[v6,3/7] target/riscv: Set endianness MSTATUS bits at CPU reset","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"49a9e136cb71fb49ffc8b26604bb0824d71886dc","submitter":{"id":90738,"url":"http://patchwork.ozlabs.org/api/people/90738/?format=json","name":"Djordje Todorovic","email":"Djordje.Todorovic@htecgroup.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260406154935.144674-4-djordje.todorovic@htecgroup.com/mbox/","series":[{"id":498877,"url":"http://patchwork.ozlabs.org/api/series/498877/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498877","date":"2026-04-06T15:49:42","name":"Add RISC-V big-endian target support","version":6,"mbox":"http://patchwork.ozlabs.org/series/498877/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2220206/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2220206/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=htecgroup.com header.i=@htecgroup.com\n header.a=rsa-sha256 header.s=selector1 header.b=KM8xcibs;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Instructions remain little-endian regardless.\n\nAlso update the disassembler comment to clarify that\nBFD_ENDIAN_LITTLE is correct because RISC-V instructions are\nalways little-endian per the ISA specification.\n\nSigned-off-by: Djordje Todorovic \n---\n target/riscv/cpu.c | 10 +++++-----\n 1 file changed, 5 insertions(+), 5 deletions(-)","diff":"diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex 4537305dfe..eed5afd27e 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -716,6 +716,9 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)\n env->mstatus = set_field(env->mstatus, MSTATUS_MDT, 1);\n }\n }\n+ if (cpu->cfg.big_endian) {\n+ env->mstatus |= MSTATUS_UBE | MSTATUS_SBE | MSTATUS_MBE;\n+ }\n env->mcause = 0;\n env->miclaim = MIP_SGEIP;\n env->pc = env->resetvec;\n@@ -803,11 +806,8 @@ static void riscv_cpu_disas_set_info(const CPUState *s, disassemble_info *info)\n info->target_info = &cpu->cfg;\n \n /*\n- * A couple of bits in MSTATUS set the endianness:\n- * - MSTATUS_UBE (User-mode),\n- * - MSTATUS_SBE (Supervisor-mode),\n- * - MSTATUS_MBE (Machine-mode)\n- * but we don't implement that yet.\n+ * RISC-V instructions are always little-endian, regardless of the\n+ * data endianness configured via MSTATUS UBE/SBE/MBE bits.\n */\n info->endian = BFD_ENDIAN_LITTLE;\n \n","prefixes":["v6","3/7"]}