{"id":2220199,"url":"http://patchwork.ozlabs.org/api/patches/2220199/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260406154935.144674-2-djordje.todorovic@htecgroup.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260406154935.144674-2-djordje.todorovic@htecgroup.com>","list_archive_url":null,"date":"2026-04-06T15:49:41","name":"[v6,1/7] target/riscv: Define MSTATUS_SBE and MSTATUS_MBE bit masks","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"3da2e5f2671c112d7085a8489f6f3966e3b086a0","submitter":{"id":90738,"url":"http://patchwork.ozlabs.org/api/people/90738/?format=json","name":"Djordje Todorovic","email":"Djordje.Todorovic@htecgroup.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260406154935.144674-2-djordje.todorovic@htecgroup.com/mbox/","series":[{"id":498877,"url":"http://patchwork.ozlabs.org/api/series/498877/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498877","date":"2026-04-06T15:49:42","name":"Add RISC-V big-endian target support","version":6,"mbox":"http://patchwork.ozlabs.org/series/498877/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2220199/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2220199/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=htecgroup.com header.i=@htecgroup.com\n header.a=rsa-sha256 header.s=selector1 header.b=jY9UaGTH;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"utf-8\"","Content-ID":"<6A81C358F35EF44188DE60D42CA0B69B@eurprd09.prod.outlook.com>","Content-Transfer-Encoding":"base64","MIME-Version":"1.0","X-OriginatorOrg":"htecgroup.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-AuthSource":"GV2PR09MB8755.eurprd09.prod.outlook.com","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n ad2dff92-cfbd-4348-b9e5-08de93f41e23","X-MS-Exchange-CrossTenant-originalarrivaltime":"06 Apr 2026 15:49:41.4602 (UTC)","X-MS-Exchange-CrossTenant-fromentityheader":"Hosted","X-MS-Exchange-CrossTenant-id":"9f85665b-7efd-4776-9dfe-b6bfda2565ee","X-MS-Exchange-CrossTenant-mailboxtype":"HOSTED","X-MS-Exchange-CrossTenant-userprincipalname":"\n W/re0g/f+uTGU/CExZC00CwSlcbbT0eMfCzBZjpFwRrZkBN77jBD0N8P+Rmx4RkCX3WiLiuL3YLjSiA4JuB7GBdhWyn0d8rv/K3wnS9Pn7M=","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"VI1PR09MB6903","Received-SPF":"pass client-ip=2a01:111:f403:c202::7;\n envelope-from=Djordje.Todorovic@htecgroup.com;\n helo=GVXPR05CU001.outbound.protection.outlook.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Add the RISC-V privileged ISA defined bit positions for the Supervisor\nBig-Endian (SBE, bit 36) and Machine Big-Endian (MBE, bit 37) fields\nin the mstatus register. These are used alongside the existing\nMSTATUS_UBE (bit 6) to control data endianness at each privilege level.\n\nThe MSTATUS_UBE definition was already present, but SBE and MBE were\nmissing.\n\nSigned-off-by: Djordje Todorovic \nReviewed-by: Philippe Mathieu-Daudé \n---\n target/riscv/cpu_bits.h | 2 ++\n 1 file changed, 2 insertions(+)","diff":"diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h\r\nindex b62dd82fe7..c2a3ee4bf3 100644\r\n--- a/target/riscv/cpu_bits.h\r\n+++ b/target/riscv/cpu_bits.h\r\n@@ -628,6 +628,8 @@\r\n #define MSTATUS_TSR 0x00400000 /* since: priv-1.10 */\r\n #define MSTATUS_SPELP 0x00800000 /* zicfilp */\r\n #define MSTATUS_SDT 0x01000000\r\n+#define MSTATUS_SBE 0x1000000000ULL\r\n+#define MSTATUS_MBE 0x2000000000ULL\r\n #define MSTATUS_MPELP 0x020000000000 /* zicfilp */\r\n #define MSTATUS_GVA 0x4000000000ULL\r\n #define MSTATUS_MPV 0x8000000000ULL\r\n","prefixes":["v6","1/7"]}