{"id":2220198,"url":"http://patchwork.ozlabs.org/api/patches/2220198/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260406154935.144674-8-djordje.todorovic@htecgroup.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260406154935.144674-8-djordje.todorovic@htecgroup.com>","list_archive_url":null,"date":"2026-04-06T15:49:43","name":"[v6,7/7] target/riscv: Add test for RISC-V BE","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"ac129919d13ccb739c9384ea00e86ea2c4cc4124","submitter":{"id":90738,"url":"http://patchwork.ozlabs.org/api/people/90738/?format=json","name":"Djordje Todorovic","email":"Djordje.Todorovic@htecgroup.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260406154935.144674-8-djordje.todorovic@htecgroup.com/mbox/","series":[{"id":498877,"url":"http://patchwork.ozlabs.org/api/series/498877/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498877","date":"2026-04-06T15:49:42","name":"Add RISC-V big-endian target support","version":6,"mbox":"http://patchwork.ozlabs.org/series/498877/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2220198/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2220198/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=htecgroup.com header.i=@htecgroup.com\n header.a=rsa-sha256 header.s=selector1 header.b=lwY+kZjY;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"iso-8859-1\"","Content-Transfer-Encoding":"quoted-printable","MIME-Version":"1.0","X-OriginatorOrg":"htecgroup.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-AuthSource":"GV2PR09MB8755.eurprd09.prod.outlook.com","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n d743d4e7-e976-4e34-419f-08de93f41f3e","X-MS-Exchange-CrossTenant-originalarrivaltime":"06 Apr 2026 15:49:43.0483 (UTC)","X-MS-Exchange-CrossTenant-fromentityheader":"Hosted","X-MS-Exchange-CrossTenant-id":"9f85665b-7efd-4776-9dfe-b6bfda2565ee","X-MS-Exchange-CrossTenant-mailboxtype":"HOSTED","X-MS-Exchange-CrossTenant-userprincipalname":"\n ZLArOYmd4eJ6Wx4mlOnKABVINOo+6sOiB0n5k29vOAoQcIC8QULOQNl4/HisIQvpsqC3nV9bSdK8tkXT9W4XVzMsOhLzlR3vgaRr9DEv8+w=","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"VI1PR09MB6903","Received-SPF":"pass client-ip=2a01:111:f403:c202::7;\n envelope-from=Djordje.Todorovic@htecgroup.com;\n helo=GVXPR05CU001.outbound.protection.outlook.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Add functional test for RISC-V big-endian.\n\nSigned-off-by: Djordje Todorovic \nReviewed-by: Thomas Huth \n---\n tests/functional/riscv64/meson.build | 1 +\n tests/functional/riscv64/test_bigendian.py | 57 ++++++++++++++++++++++\n 2 files changed, 58 insertions(+)\n create mode 100644 tests/functional/riscv64/test_bigendian.py","diff":"diff --git a/tests/functional/riscv64/meson.build b/tests/functional/riscv64/meson.build\nindex b996c89d7d..d06d6ea112 100644\n--- a/tests/functional/riscv64/meson.build\n+++ b/tests/functional/riscv64/meson.build\n@@ -11,6 +11,7 @@ tests_riscv64_system_quick = [\n ]\n \n tests_riscv64_system_thorough = [\n+ 'bigendian',\n 'boston',\n 'sifive_u',\n 'tuxrun',\ndiff --git a/tests/functional/riscv64/test_bigendian.py b/tests/functional/riscv64/test_bigendian.py\nnew file mode 100644\nindex 0000000000..9e0b3b7db5\n--- /dev/null\n+++ b/tests/functional/riscv64/test_bigendian.py\n@@ -0,0 +1,57 @@\n+#!/usr/bin/env python3\n+#\n+# Functional tests for RISC-V big-endian support\n+#\n+# Copyright (c) 2026 MIPS\n+#\n+# SPDX-License-Identifier: GPL-2.0-or-later\n+\n+from qemu_test import QemuSystemTest, Asset\n+from qemu_test import wait_for_console_pattern\n+\n+\n+class RiscvBigEndian(QemuSystemTest):\n+ \"\"\"\n+ Tests for RISC-V runtime big-endian data support.\n+\n+ Uses a bare-metal RV64 ELF that detects data endianness at runtime\n+ by storing a 32-bit word and reading back byte 0. Prints \"ENDIAN: BE\"\n+ or \"ENDIAN: LE\" to the NS16550A UART on the virt machine.\n+ \"\"\"\n+\n+ timeout = 10\n+\n+ ASSET_BE_TEST = Asset(\n+ 'https://github.com/MIPS/linux-test-downloads/raw/main/'\n+ 'riscvbe-baremetal/be-test-bare-metal.elf',\n+ '9ad51b675e101de65908fadbac064ed1d0564c17463715d09dd734db86ea0f58')\n+\n+ def _run_bare_metal(self, big_endian=False):\n+ self.set_machine('virt')\n+ kernel = self.ASSET_BE_TEST.fetch()\n+ self.vm.add_args('-bios', 'none')\n+ self.vm.add_args('-kernel', kernel)\n+ if big_endian:\n+ self.vm.add_args('-cpu', 'rv64,big-endian=on')\n+ self.vm.set_console()\n+ self.vm.launch()\n+ expected = 'ENDIAN: BE' if big_endian else 'ENDIAN: LE'\n+ wait_for_console_pattern(self, expected)\n+\n+ def test_bare_metal_littleendian(self):\n+ \"\"\"\n+ Boot bare-metal ELF on virt with default little-endian CPU.\n+ Expects \"ENDIAN: LE\" on UART.\n+ \"\"\"\n+ self._run_bare_metal(big_endian=False)\n+\n+ def test_bare_metal_bigendian(self):\n+ \"\"\"\n+ Boot bare-metal ELF on virt with big-endian=on CPU property.\n+ Expects \"ENDIAN: BE\" on UART.\n+ \"\"\"\n+ self._run_bare_metal(big_endian=True)\n+\n+\n+if __name__ == '__main__':\n+ QemuSystemTest.main()\n","prefixes":["v6","7/7"]}