{"id":2220197,"url":"http://patchwork.ozlabs.org/api/patches/2220197/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260406154935.144674-3-djordje.todorovic@htecgroup.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260406154935.144674-3-djordje.todorovic@htecgroup.com>","list_archive_url":null,"date":"2026-04-06T15:49:41","name":"[v6,2/7] target/riscv: Add big-endian CPU property","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"3a4d73c2d96c831265508d58a67d4a63ffa2a429","submitter":{"id":90738,"url":"http://patchwork.ozlabs.org/api/people/90738/?format=json","name":"Djordje Todorovic","email":"Djordje.Todorovic@htecgroup.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260406154935.144674-3-djordje.todorovic@htecgroup.com/mbox/","series":[{"id":498877,"url":"http://patchwork.ozlabs.org/api/series/498877/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498877","date":"2026-04-06T15:49:42","name":"Add RISC-V big-endian target support","version":6,"mbox":"http://patchwork.ozlabs.org/series/498877/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2220197/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2220197/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=htecgroup.com header.i=@htecgroup.com\n header.a=rsa-sha256 header.s=selector1 header.b=ehyADqDr;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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This property allows machine\nmodels to configure individual HARTs for big-endian data operation.\n\nThe RISC-V ISA supports big-endian data accesses via the mstatus\nSBE/MBE/UBE bits, while instructions remain always little-endian.\nThis property provides the configuration interface; subsequent\npatches will connect it to the CPU state and translation logic.\n\nSigned-off-by: Djordje Todorovic \nReviewed-by: Chao Liu \n---\n target/riscv/cpu.c | 1 +\n target/riscv/cpu_cfg_fields.h.inc | 1 +\n 2 files changed, 2 insertions(+)","diff":"diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex e56470a374..4537305dfe 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -2641,6 +2641,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {\n \n static const Property riscv_cpu_properties[] = {\n DEFINE_PROP_BOOL(\"debug\", RISCVCPU, cfg.debug, true),\n+ DEFINE_PROP_BOOL(\"big-endian\", RISCVCPU, cfg.big_endian, false),\n \n {.name = \"pmu-mask\", .info = &prop_pmu_mask},\n {.name = \"pmu-num\", .info = &prop_pmu_num}, /* Deprecated */\ndiff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc\nindex 70ec650abf..51436daabf 100644\n--- a/target/riscv/cpu_cfg_fields.h.inc\n+++ b/target/riscv/cpu_cfg_fields.h.inc\n@@ -154,6 +154,7 @@ BOOL_FIELD(ext_xmipscbop)\n BOOL_FIELD(ext_xmipscmov)\n BOOL_FIELD(ext_xmipslsp)\n \n+BOOL_FIELD(big_endian)\n BOOL_FIELD(mmu)\n BOOL_FIELD(pmp)\n BOOL_FIELD(debug)\n","prefixes":["v6","2/7"]}