{"id":2220171,"url":"http://patchwork.ozlabs.org/api/patches/2220171/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260406150434.407201-5-pierrick.bouvier@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260406150434.407201-5-pierrick.bouvier@linaro.org>","list_archive_url":null,"date":"2026-04-06T15:04:24","name":"[v7,04/14] target/arm/tcg/translate.h: remove TARGET_AARCH64","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"083101e3541b4dfd11c7dda574ab1a0bd6092766","submitter":{"id":85798,"url":"http://patchwork.ozlabs.org/api/people/85798/?format=json","name":"Pierrick Bouvier","email":"pierrick.bouvier@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260406150434.407201-5-pierrick.bouvier@linaro.org/mbox/","series":[{"id":498869,"url":"http://patchwork.ozlabs.org/api/series/498869/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498869","date":"2026-04-06T15:04:20","name":"target/arm: single-binary","version":7,"mbox":"http://patchwork.ozlabs.org/series/498869/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2220171/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2220171/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=dI63pOJa;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::62b;\n envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x62b.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"We need to stub a64_translate_init and gen_a64_update_pc.\nAt this point, we don't need to do anything for aarch64_translator_ops\nsince it's just an external symbol.\n\nWe can now include target/arm/tcg/translate.h from common code, since\nall target specific bits have been removed, or can be specialized with\nspecific defines.\n\nReviewed-by: Philippe Mathieu-Daudé \nReviewed-by: Richard Henderson \nSigned-off-by: Pierrick Bouvier \n---\n target/arm/tcg/translate.h | 10 ----------\n target/arm/tcg/stubs32.c | 17 +++++++++++++++++\n target/arm/tcg/meson.build | 1 +\n 3 files changed, 18 insertions(+), 10 deletions(-)\n create mode 100644 target/arm/tcg/stubs32.c","diff":"diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h\nindex e28eac54afb..77fdc5f3a17 100644\n--- a/target/arm/tcg/translate.h\n+++ b/target/arm/tcg/translate.h\n@@ -357,19 +357,9 @@ static inline int curr_insn_len(DisasContext *s)\n /* CPU state was modified dynamically; no need to exit, but do not chain. */\n #define DISAS_UPDATE_NOCHAIN DISAS_TARGET_10\n \n-#ifdef TARGET_AARCH64\n void a64_translate_init(void);\n void gen_a64_update_pc(DisasContext *s, int64_t diff);\n extern const TranslatorOps aarch64_translator_ops;\n-#else\n-static inline void a64_translate_init(void)\n-{\n-}\n-\n-static inline void gen_a64_update_pc(DisasContext *s, int64_t diff)\n-{\n-}\n-#endif\n \n void arm_test_cc(DisasCompare *cmp, int cc);\n void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);\ndiff --git a/target/arm/tcg/stubs32.c b/target/arm/tcg/stubs32.c\nnew file mode 100644\nindex 00000000000..c5a0bc61f47\n--- /dev/null\n+++ b/target/arm/tcg/stubs32.c\n@@ -0,0 +1,17 @@\n+/*\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"target/arm/tcg/translate.h\"\n+\n+\n+void gen_a64_update_pc(DisasContext *s, int64_t diff)\n+{\n+ g_assert_not_reached();\n+}\n+\n+void a64_translate_init(void)\n+{\n+ /* Don't initialize for 32 bits. Call site will be fixed later. */\n+}\ndiff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build\nindex 5f591560551..3e96c77df73 100644\n--- a/target/arm/tcg/meson.build\n+++ b/target/arm/tcg/meson.build\n@@ -21,6 +21,7 @@ gen_a32 = [\n \n arm_ss.add(gen_a32)\n arm_ss.add(when: 'TARGET_AARCH64', if_true: gen_a64)\n+arm_ss.add(when: 'TARGET_AARCH64', if_false: files('stubs32.c'))\n \n arm_ss.add(files(\n 'cpu32.c',\n","prefixes":["v7","04/14"]}