{"id":2220061,"url":"http://patchwork.ozlabs.org/api/patches/2220061/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260406075114.25672-3-clamor95@gmail.com/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260406075114.25672-3-clamor95@gmail.com>","list_archive_url":null,"date":"2026-04-06T07:51:14","name":"[v5,2/2] dt-bindings: pinctrl: pinctrl-max77620: convert to DT schema","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"ae2a4d14265c4aca42037cc3cc208dc56deb8fc3","submitter":{"id":84146,"url":"http://patchwork.ozlabs.org/api/people/84146/?format=json","name":"Svyatoslav Ryhel","email":"clamor95@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260406075114.25672-3-clamor95@gmail.com/mbox/","series":[{"id":498830,"url":"http://patchwork.ozlabs.org/api/series/498830/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=498830","date":"2026-04-06T07:51:12","name":"rtc: max77686: convert to i2c_new_ancillary_device","version":5,"mbox":"http://patchwork.ozlabs.org/series/498830/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2220061/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2220061/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=d6EZuyg2;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-gpio+bounces-34699-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com\n header.b=\"d6EZuyg2\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=209.85.128.49","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=gmail.com"],"Received":["from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fq1kk4z8Yz1y2d\n\tfor ; Mon, 06 Apr 2026 17:52:14 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby tor.lore.kernel.org (Postfix) with ESMTP id 7E84A301875D\n\tfor ; Mon, 6 Apr 2026 07:51:38 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id D749F373C1A;\n\tMon, 6 Apr 2026 07:51:32 +0000 (UTC)","from mail-wm1-f49.google.com (mail-wm1-f49.google.com\n [209.85.128.49])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id F074C366DC0\n\tfor ; Mon, 6 Apr 2026 07:51:30 +0000 (UTC)","by mail-wm1-f49.google.com with SMTP id\n 5b1f17b1804b1-488b00ed86fso7284755e9.3\n for ;\n Mon, 06 Apr 2026 00:51:30 -0700 (PDT)","from xeon ([188.163.112.56])\n by smtp.gmail.com with ESMTPSA id\n 5b1f17b1804b1-488b739e00bsm20393525e9.10.2026.04.06.00.51.28\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Mon, 06 Apr 2026 00:51:28 -0700 (PDT)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1775461892; cv=none;\n b=sbSBNm9skME2OqkOt/qkj6DUr6cHvlua1Ieg7xjkNcqm68gxG/fYxbkG1dci+w/41LkUdOGgtkf89sV8qo5tQWL2tETc9NjN86DY0Ks8A0f+RDffYyoqbVlz692n6YWr6f3gcG3XVXbkxnzXSqBI58mHDXilbTWWu9/s2+NnZS4=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1775461892; c=relaxed/simple;\n\tbh=6QiwAReXTpBojlHHp4n5juTw3CiqRhW6QKlsg4KCdoc=;\n\th=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version;\n b=cDBiP+5MhADK98PJ+xpmacQ3bvtwKsrOK67amQQlMTJDl+iCA7zIqLyEwrPCM7ls1Vn8uJdFOdXMTSgZjOyIWvqYKFuAPI7BaarxKuZ5PStZkh42vX43V3MoZCZv/LGca5CH2oOhxXKrZaVnh51h9proWSKDfs4P9O0bsQickko=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com;\n spf=pass smtp.mailfrom=gmail.com;\n dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com\n header.b=d6EZuyg2; arc=none smtp.client-ip=209.85.128.49","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=gmail.com; s=20251104; t=1775461889; x=1776066689;\n darn=vger.kernel.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=H1yRoOrwamurkh8iKC4rWIAOsL7TI+/4XONPPGFJ1VM=;\n b=d6EZuyg2H7GTsIHA+AbH5zFB9tZ/peLTW4aUKZXbem23j6Xoa+/k6DUCZfS1APvvHN\n 5MODVOZV8Iqz7nsFX9n/XM5xig8uL2gks3eKEd7Qb7VAmD5NtkenlvlOd9UoM3eYeYIH\n xsSjSE2F668w0u0P/K1+1oDzpdLTjRpPr3yPRZhBNevAF213233DfgYUr1Z/r1/W0I62\n jdxHiCOyhSMjRvm1Gt2WmP72Q5Gl8scYngrLbvj7iRNVaHpFHwlKr2sjABA5btMDP136\n 31qWlu57Eqm9A5Z8NOD0C79BGRY2ZkLnM4CESHk07HCHWAoGkv+NPln8o19wRsVye5bU\n jgpQ==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1775461889; x=1776066689;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=H1yRoOrwamurkh8iKC4rWIAOsL7TI+/4XONPPGFJ1VM=;\n b=XT9tmxzRLjkj8j76Tjm/g44uUBgc3heOWl8+0I2fKTCDbKJG4cOxwn/l0C35VBJJcG\n 1ShCgL2HT3apOOXu+435qYdzTrXKayiwJr78ciXllGfUqZpBdjO7TYWqZTy94dnBwySi\n kbS5jSoWyZsd4H4+2rC9Xc8wxZSd6gLUERuMu6w1aQA/5t1ice+hzkhI0gx9ZzN4DWDc\n Pv+749ftA7IdzxJVIEbGCoh/SekaZL/kk0p/QaNtOwVTiqUe2YaBRrfKSc4PH+mtdbTu\n ntT3MpAz0MUuIYKAvDois+KtqQK0Ec/OxEVIk34WrotOKt7cM6F+aAl3OM24kAUvDZnc\n Ag3w==","X-Gm-Message-State":"AOJu0YzoGdMWN+wM3Wz6Qusn8tg7beTLd66+aTErin2WrpUiqtBM3N3n\n\tvdiHV/VBo7NDWQ9LhnYSKFr3pttRCWCrEy4LDa6jknPXqeydWIdPZmFk","X-Gm-Gg":"AeBDievmxN6hq55bHeQAz4zTUl58uaAGvq+9DmukiQoxObR5mUKV7rkEKndi3deL7ud\n\t7D7zLKhyqcK+PCa1ONzRgPVUXDkJ8bY8WnORN0DpjXjauI51n5Z+5qD+mNIAXtWMLt/qKDwAAqv\n\tslP1haE3+j877FoPbSDgHlHUN7u151sNfB0G63RXLKzHtY6r/aCKTOtKxbpOc85KJhD7ftOxpWW\n\teDMRzWUT5763jWwXo1G1ZwEJ79hFVtEAzQr49H41+DWeVC6ln8eBjnrp25smo/dCuoNQr0pHIzw\n\trpCckxWzNgsTJhEuEF2IEhkHOiCQpa79cvFUUDHCB0dNbssL8XAzFLwQ36mRG3ApjN/vNiXIQdv\n\tI4Cy4VmCPxYGmnANu2isPS6uHIoFXDMgiBKaa39JnZJVuLKkLyWwOi0AkW+wQcaLXxfznYYJ9tV\n\tdfAoYNLmmomORX","X-Received":"by 2002:a05:600c:3048:b0:488:9bf8:7f17 with SMTP id\n 5b1f17b1804b1-4889bf8821fmr94252615e9.14.1775461889025;\n Mon, 06 Apr 2026 00:51:29 -0700 (PDT)","From":"Svyatoslav Ryhel ","To":"Linus Walleij ,\n\tRob Herring ,\n\tKrzysztof Kozlowski ,\n\tConor Dooley ,\n\tLiam Girdwood ,\n\tMark Brown ,\n\tSvyatoslav Ryhel ","Cc":"linux-gpio@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org","Subject":"[PATCH v5 2/2] dt-bindings: pinctrl: pinctrl-max77620: convert to DT\n schema","Date":"Mon, 6 Apr 2026 10:51:14 +0300","Message-ID":"<20260406075114.25672-3-clamor95@gmail.com>","X-Mailer":"git-send-email 2.51.0","In-Reply-To":"<20260406075114.25672-1-clamor95@gmail.com>","References":"<20260406075114.25672-1-clamor95@gmail.com>","Precedence":"bulk","X-Mailing-List":"linux-gpio@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit"},"content":"Convert pinctrl-max77620 devicetree bindings for the MAX77620 PMIC from\nTXT to YAML format. This patch does not change any functionality; the\nbindings remain the same.\n\nSigned-off-by: Svyatoslav Ryhel \n---\n .../pinctrl/maxim,max77620-pinctrl.yaml | 98 ++++++++++++++\n .../bindings/pinctrl/pinctrl-max77620.txt | 127 ------------------\n 2 files changed, 98 insertions(+), 127 deletions(-)\n create mode 100644 Documentation/devicetree/bindings/pinctrl/maxim,max77620-pinctrl.yaml\n delete mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt","diff":"diff --git a/Documentation/devicetree/bindings/pinctrl/maxim,max77620-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/maxim,max77620-pinctrl.yaml\nnew file mode 100644\nindex 000000000000..b3ea36474317\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/maxim,max77620-pinctrl.yaml\n@@ -0,0 +1,98 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pinctrl/maxim,max77620-pinctrl.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Pinmux controller function for Maxim MAX77620 Power management IC\n+\n+maintainers:\n+ - Svyatoslav Ryhel \n+\n+description:\n+ Device has 8 GPIO pins which can be configured as GPIO as well as the\n+ special IO functions.\n+\n+allOf:\n+ - $ref: /schemas/pinctrl/pincfg-node.yaml\n+ - $ref: /schemas/pinctrl/pinmux-node.yaml\n+\n+patternProperties:\n+ \"^(pin|gpio).\":\n+ type: object\n+ additionalProperties: false\n+\n+ properties:\n+ pins:\n+ items:\n+ enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7 ]\n+\n+ function:\n+ items:\n+ enum: [ gpio, lpm-control-in, fps-out, 32k-out1, sd0-dvs-in, sd1-dvs-in,\n+ reference-out ]\n+\n+ drive-push-pull: true\n+ drive-open-drain: true\n+ bias-pull-up: true\n+ bias-pull-down: true\n+\n+ maxim,active-fps-source:\n+ $ref: /schemas/types.yaml#/definitions/uint32\n+ description: |\n+ FPS source for the GPIOs to get enabled/disabled when system is in\n+ active state. Valid values are:\n+ - MAX77620_FPS_SRC_0: FPS source is FPS0.\n+ - MAX77620_FPS_SRC_1: FPS source is FPS1\n+ - MAX77620_FPS_SRC_2: FPS source is FPS2\n+ - MAX77620_FPS_SRC_NONE: GPIO is not controlled by FPS events and\n+ it gets enabled/disabled by register access.\n+ Absence of this property will leave the FPS configuration register\n+ for that GPIO to default configuration.\n+\n+ maxim,active-fps-power-up-slot:\n+ $ref: /schemas/types.yaml#/definitions/uint32\n+ description:\n+ Sequencing event slot number on which the GPIO get enabled when\n+ master FPS input event set to HIGH. This is applicable if FPS source\n+ is selected as FPS0, FPS1 or FPS2.\n+ enum: [0, 1, 2, 3, 4, 5, 6, 7]\n+\n+ maxim,active-fps-power-down-slot:\n+ $ref: /schemas/types.yaml#/definitions/uint32\n+ description:\n+ Sequencing event slot number on which the GPIO get disabled when\n+ master FPS input event set to LOW. This is applicable if FPS source\n+ is selected as FPS0, FPS1 or FPS2.\n+ enum: [0, 1, 2, 3, 4, 5, 6, 7]\n+\n+ maxim,suspend-fps-source:\n+ $ref: /schemas/types.yaml#/definitions/uint32\n+ description:\n+ This is same as property \"maxim,active-fps-source\" but value get\n+ configured when system enters in to suspend state.\n+\n+ maxim,suspend-fps-power-up-slot:\n+ $ref: /schemas/types.yaml#/definitions/uint32\n+ description:\n+ This is same as property \"maxim,active-fps-power-up-slot\" but this\n+ value get configured into FPS configuration register when system\n+ enters into suspend. This is applicable if suspend state FPS source\n+ is selected as FPS0, FPS1 or FPS2.\n+ enum: [0, 1, 2, 3, 4, 5, 6, 7]\n+\n+ maxim,suspend-fps-power-down-slot:\n+ $ref: /schemas/types.yaml#/definitions/uint32\n+ description:\n+ This is same as property \"maxim,active-fps-power-down-slot\" but this\n+ value get configured into FPS configuration register when system\n+ enters into suspend. This is applicable if suspend state FPS source\n+ is selected as FPS0, FPS1 or FPS2.\n+ enum: [0, 1, 2, 3, 4, 5, 6, 7]\n+\n+ required:\n+ - pins\n+\n+additionalProperties: false\n+\n+# see maxim,max77620.yaml for an example\ndiff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt\ndeleted file mode 100644\nindex 28fbca180068..000000000000\n--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt\n+++ /dev/null\n@@ -1,127 +0,0 @@\n-Pincontrol driver for MAX77620 Power management IC from Maxim Semiconductor.\n-\n-Device has 8 GPIO pins which can be configured as GPIO as well as the\n-special IO functions.\n-\n-Please refer file \n-for details of the common pinctrl bindings used by client devices,\n-including the meaning of the phrase \"pin configuration node\".\n-\n-Optional Pinmux properties:\n---------------------------\n-Following properties are required if default setting of pins are required\n-at boot.\n-- pinctrl-names: A pinctrl state named per .\n-- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per\n-\t\t.\n-\n-The pin configurations are defined as child of the pinctrl states node. Each\n-sub-node have following properties:\n-\n-Required properties:\n-------------------\n-- pins: List of pins. Valid values of pins properties are:\n-\t\t gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7.\n-\n-Optional properties:\n--------------------\n-Following are optional properties defined as pinmux DT binding document\n-. Absence of properties will leave the configuration\n-on default.\n-\tfunction,\n-\tdrive-push-pull,\n-\tdrive-open-drain,\n-\tbias-pull-up,\n-\tbias-pull-down.\n-\n-Valid values for function properties are:\n-\tgpio, lpm-control-in, fps-out, 32k-out, sd0-dvs-in, sd1-dvs-in,\n-\treference-out\n-\n-There are also customised properties for the GPIO1, GPIO2 and GPIO3. These\n-customised properties are required to configure FPS configuration parameters\n-of these GPIOs. Please refer for more\n-detail of Flexible Power Sequence (FPS).\n-\n-- maxim,active-fps-source:\t\tFPS source for the GPIOs to get\n-\t\t\t\t\tenabled/disabled when system is in\n-\t\t\t\t\tactive state. Valid values are:\n-\t\t\t\t\t- MAX77620_FPS_SRC_0,\n-\t\t\t\t\t\tFPS source is FPS0.\n-\t\t\t\t\t- MAX77620_FPS_SRC_1,\n-\t\t\t\t\t\tFPS source is FPS1\n-\t\t\t\t\t- MAX77620_FPS_SRC_2 and\n-\t\t\t\t\t\tFPS source is FPS2\n-\t\t\t\t\t- MAX77620_FPS_SRC_NONE.\n-\t\t\t\t\t\tGPIO is not controlled\n-\t\t\t\t\t\tby FPS events and it gets\n-\t\t\t\t\t\tenabled/disabled by register\n-\t\t\t\t\t\taccess.\n-\t\t\t\t\tAbsence of this property will leave\n-\t\t\t\t\tthe FPS configuration register for that\n-\t\t\t\t\tGPIO to default configuration.\n-\n-- maxim,active-fps-power-up-slot:\tSequencing event slot number on which\n-\t\t\t\t\tthe GPIO get enabled when\n-\t\t\t\t\tmaster FPS input event set to HIGH.\n-\t\t\t\t\tValid values are 0 to 7.\n-\t\t\t\t\tThis is applicable if FPS source is\n-\t\t\t\t\tselected as FPS0, FPS1 or FPS2.\n-\n-- maxim,active-fps-power-down-slot:\tSequencing event slot number on which\n-\t\t\t\t\tthe GPIO get disabled when master\n-\t\t\t\t\tFPS input event set to LOW.\n-\t\t\t\t\tValid values are 0 to 7.\n-\t\t\t\t\tThis is applicable if FPS source is\n-\t\t\t\t\tselected as FPS0, FPS1 or FPS2.\n-\n-- maxim,suspend-fps-source:\t\tThis is same as property\n-\t\t\t\t\t\"maxim,active-fps-source\" but value\n-\t\t\t\t\tget configured when system enters in\n-\t\t\t\t\tto suspend state.\n-\n-- maxim,suspend-fps-power-up-slot:\tThis is same as property\n-\t\t\t\t\t\"maxim,active-fps-power-up-slot\" but\n-\t\t\t\t\tthis value get configured into FPS\n-\t\t\t\t\tconfiguration register when system\n-\t\t\t\t\tenters into suspend.\n-\t\t\t\t\tThis is applicable if suspend state\n-\t\t\t\t\tFPS source is selected as FPS0, FPS1 or\n-\n-- maxim,suspend-fps-power-down-slot:\tThis is same as property\n-\t\t\t\t\t\"maxim,active-fps-power-down-slot\" but\n-\t\t\t\t\tthis value get configured into FPS\n-\t\t\t\t\tconfiguration register when system\n-\t\t\t\t\tenters into suspend.\n-\t\t\t\t\tThis is applicable if suspend state\n-\t\t\t\t\tFPS source is selected as FPS0, FPS1 or\n-\t\t\t\t\tFPS2.\n-\n-Example:\n---------\n-#include \n-...\n-max77620@3c {\n-\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&spmic_default>;\n-\n-\tspmic_default: pinmux@0 {\n-\t\tpin_gpio0 {\n-\t\t\tpins = \"gpio0\";\n-\t\t\tfunction = \"gpio\";\n-\t\t};\n-\n-\t\tpin_gpio1 {\n-\t\t\tpins = \"gpio1\";\n-\t\t\tfunction = \"fps-out\";\n-\t\t\tmaxim,active-fps-source = ;\n-\t\t};\n-\n-\t\tpin_gpio2 {\n-\t\t\tpins = \"gpio2\";\n-\t\t\tfunction = \"fps-out\";\n-\t\t\tmaxim,active-fps-source = ;\n-\t\t};\n-\t};\n-};\n","prefixes":["v5","2/2"]}