{"id":2219762,"url":"http://patchwork.ozlabs.org/api/patches/2219762/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260404-t_power_on_fux-v4-1-2891391177f4@oss.qualcomm.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260404-t_power_on_fux-v4-1-2891391177f4@oss.qualcomm.com>","list_archive_url":null,"date":"2026-04-04T08:17:18","name":"[v4,1/3] PCI/ASPM: Add helper to encode L1SS T_POWER_ON fields","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"b57d9589a1938046141ad4f702044dcbf06a3d4d","submitter":{"id":89908,"url":"http://patchwork.ozlabs.org/api/people/89908/?format=json","name":"Krishna Chaitanya Chundru","email":"krishna.chundru@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260404-t_power_on_fux-v4-1-2891391177f4@oss.qualcomm.com/mbox/","series":[{"id":498705,"url":"http://patchwork.ozlabs.org/api/series/498705/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=498705","date":"2026-04-04T08:17:17","name":"PCI: qcom: Program T_POWER_ON value for L1.2 exit timing","version":4,"mbox":"http://patchwork.ozlabs.org/series/498705/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2219762/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2219762/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=hWZawlGM;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=D2TnIY9j;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260404-t_power_on_fux-v4-1-2891391177f4@oss.qualcomm.com>","References":"<20260404-t_power_on_fux-v4-0-2891391177f4@oss.qualcomm.com>","In-Reply-To":"<20260404-t_power_on_fux-v4-0-2891391177f4@oss.qualcomm.com>","To":"Manivannan Sadhasivam ,\n Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= , Rob Herring ,\n Bjorn Helgaas , Jingoo Han ","Cc":"linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org,\n linux-kernel@vger.kernel.org, mayank.rana@oss.qualcomm.com,\n quic_vbadigan@quicinc.com,\n Krishna Chaitanya Chundru ,\n Shawn Lin ","X-Mailer":"b4 0.14.2","X-Developer-Signature":"v=1; a=ed25519-sha256; t=1775290641; l=3804;\n i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id;\n bh=dN9KuR0kzkXGKzvIaarHHedGIsZ1F9GAhzyZs0HPCMY=;\n b=W2NXnHDHFweweqMbY5/CM39de3U6WWWxKMRBY3t7odo7sqwmMVkUW0GNJ+pJxjUMQF1yoEda2\n n4BYSzEGocmCl3uxvUy1zO029yix+lo9h4GYegcnkX1HNE3JJYe+WTh","X-Developer-Key":"i=krishna.chundru@oss.qualcomm.com; a=ed25519;\n pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg=","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDA0MDA3MiBTYWx0ZWRfX6afaBM5osaaI\n 3jPkHviRUe0ZRk/wioXDgCz8Hhg8UXqwageJr92jK9wd7vBOFu9KSnOTe749Y4sdc4uiArP37T4\n KpO1+jKEivGGjzetr/bBHedKzIEMyHDC6pgVCIMgbiXV0n1CuoTNN8df4jIysBr6uoPhopbqYhF\n ZOF5RTfmrv4RIIAN1pic9nOjGBPTGgjYKUoqsg3sHRQlRECiLS4UtPatu+Fx6fgUXtjc7PPHk+C\n ufPC0UKDtk7iH6mP2UQVKFSybjtzCEzu2x3urKuVSlv4ralDr7vksV9eduTxJvofmcp2AjzzIz8\n akq8p3ES+jX6mIrMXswX+H917KN58RKIie0llo3JyDQ2JqPCoeYmzNljOva6HvWSwkeigN9zr3o\n 5A8pzilqRw1WFglV2XYHE6TCYTS8DwMLv0qnPYMAUEBW9uN9is378ChZ9+O+Jy2k374l0Q8PDFN\n XcqlYUhPH30g760uyag==","X-Proofpoint-ORIG-GUID":"jI5lTwcrruc5BILJYfv2zMh27BLAX7HI","X-Proofpoint-GUID":"jI5lTwcrruc5BILJYfv2zMh27BLAX7HI","X-Authority-Analysis":"v=2.4 cv=I6Zohdgg c=1 sm=1 tr=0 ts=69d0c91b cx=c_pps\n a=rz3CxIlbcmazkYymdCej/Q==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22\n a=s8YR1HE3AAAA:8 a=EUspDBNiAAAA:8 a=j3416i00YO8nPnzCGbIA:9 a=QEXdDO2ut3YA:10\n a=bFCP_H2QrGi7Okbo017w:22 a=jGH_LyMDp9YhSvY-UuyI:22","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-03_07,2026-04-03_01,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n adultscore=0 impostorscore=0 suspectscore=0 spamscore=0 priorityscore=1501\n malwarescore=0 bulkscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604040072"},"content":"Add a shared helper to encode the PCIe L1 PM Substates T_POWER_ON\nparameter into the T_POWER_ON Scale and T_POWER_ON Value fields.\n\nThis helper can be used by the controller drivers to change the\ndefault/wrong value of T_POWER_ON in L1ss capability register to\navoid incorrect calculation of LTR_L1.2_THRESHOLD value.\n\nThe helper converts a T_POWER_ON time specified in microseconds into\nthe appropriate scale/value encoding defined by the PCIe spec r7.0,\nsec 7.8.3.2. Values that exceed the maximum encodable range are clamped\nto the largest representable encoding.\n\nTested-by: Shawn Lin \nReviewed-by: Shawn Lin \nSigned-off-by: Krishna Chaitanya Chundru \n---\n drivers/pci/pci.h | 2 ++\n drivers/pci/pcie/aspm.c | 40 ++++++++++++++++++++++++++++++++++++++++\n 2 files changed, 42 insertions(+)","diff":"diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h\nindex 13d998fbacce6698514d92500dfea03cc562cdc2..48964602d802e114a6a2481df3fb75d9e178a31b 100644\n--- a/drivers/pci/pci.h\n+++ b/drivers/pci/pci.h\n@@ -1105,6 +1105,7 @@ void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked);\n void pcie_aspm_powersave_config_link(struct pci_dev *pdev);\n void pci_configure_ltr(struct pci_dev *pdev);\n void pci_bridge_reconfigure_ltr(struct pci_dev *pdev);\n+void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8 *value);\n #else\n static inline void pcie_aspm_remove_cap(struct pci_dev *pdev, u32 lnkcap) { }\n static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }\n@@ -1113,6 +1114,7 @@ static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked)\n static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }\n static inline void pci_configure_ltr(struct pci_dev *pdev) { }\n static inline void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) { }\n+static inline void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8 *value) { }\n #endif\n \n #ifdef CONFIG_PCIE_ECRC\ndiff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c\nindex 21f5d23e0b61bd7e1163cc869fe9356d1ab87b34..879d7ecddf8d6430c49f31c88a75d5c6e74015d6 100644\n--- a/drivers/pci/pcie/aspm.c\n+++ b/drivers/pci/pcie/aspm.c\n@@ -525,6 +525,46 @@ static u32 calc_l12_pwron(struct pci_dev *pdev, u32 scale, u32 val)\n \treturn 0;\n }\n \n+/**\n+ * pcie_encode_t_power_on - Encode T_POWER_ON into scale and value fields\n+ * @t_power_on_us: T_POWER_ON time in microseconds\n+ * @scale: Encoded T_POWER_ON Scale (0..2)\n+ * @value: Encoded T_POWER_ON Value\n+ *\n+ * T_POWER_ON is encoded as:\n+ * T_POWER_ON(us) = scale_unit(us) * value\n+ *\n+ * where scale_unit is selected by @scale:\n+ * 0: 2us\n+ * 1: 10us\n+ * 2: 100us\n+ *\n+ * If @t_power_on_us exceeds the maximum representable value, the result\n+ * is clamped to the largest encodable T_POWER_ON.\n+ *\n+ * See PCIe r7.0, sec 7.8.3.2.\n+ */\n+void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8 *value)\n+{\n+\tu8 maxv = FIELD_MAX(PCI_L1SS_CAP_P_PWR_ON_VALUE);\n+\n+\t/* T_POWER_ON_Value (\"value\") is a 5-bit field with max value of 31. */\n+\tif (t_power_on_us <= 2 * maxv) {\n+\t\t*scale = 0; /* Value times 2us */\n+\t\t*value = DIV_ROUND_UP(t_power_on_us, 2);\n+\t} else if (t_power_on_us <= 10 * maxv) {\n+\t\t*scale = 1; /* Value times 10us */\n+\t\t*value = DIV_ROUND_UP(t_power_on_us, 10);\n+\t} else if (t_power_on_us <= 100 * maxv) {\n+\t\t*scale = 2; /* value times 100us */\n+\t\t*value = DIV_ROUND_UP(t_power_on_us, 100);\n+\t} else {\n+\t\t*scale = 2;\n+\t\t*value = maxv;\n+\t}\n+}\n+EXPORT_SYMBOL(pcie_encode_t_power_on);\n+\n /*\n * Encode an LTR_L1.2_THRESHOLD value for the L1 PM Substates Control 1\n * register. Ports enter L1.2 when the most recent LTR value is greater\n","prefixes":["v4","1/3"]}