{"id":2219743,"url":"http://patchwork.ozlabs.org/api/patches/2219743/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260404042015.86580-3-mohamed@unpredictable.fr/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260404042015.86580-3-mohamed@unpredictable.fr>","list_archive_url":null,"date":"2026-04-04T04:20:06","name":"[v6,02/11] whpx: i386: x2apic emulation","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"ebac3004b414e1e140587e833b3fa5c9dcb9877e","submitter":{"id":91318,"url":"http://patchwork.ozlabs.org/api/people/91318/?format=json","name":"Mohamed Mediouni","email":"mohamed@unpredictable.fr"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260404042015.86580-3-mohamed@unpredictable.fr/mbox/","series":[{"id":498696,"url":"http://patchwork.ozlabs.org/api/series/498696/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498696","date":"2026-04-04T04:20:05","name":"whpx: i386: bug fixes, feature probing and CPUID","version":6,"mbox":"http://patchwork.ozlabs.org/series/498696/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2219743/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2219743/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=unpredictable.fr header.i=@unpredictable.fr\n header.a=rsa-sha256 header.s=sig1 header.b=fz8bzEf4;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=outbound.st.icloud.com","X-Spam_score_int":"-27","X-Spam_score":"-2.8","X-Spam_bar":"--","X-Spam_report":"(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Add x2apic emulation to WHPX for the kernel-irqchip=off case.\n\nUnfortunately, it looks like there isn't a workaround available\nfor proper behavior of PIC interrupts when kernel-irqchip=on\nfor Windows 10. The OS is out of support outside of extended\nsecurity updates so this will not be addressed.\n\nThe performance boost is quite visible for multicore guests.\n\nSigned-off-by: Mohamed Mediouni \n---\n target/i386/whpx/whpx-all.c | 134 +++++++++++++++++++++++++++++++++++-\n 1 file changed, 133 insertions(+), 1 deletion(-)","diff":"diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c\nindex e56ae2b343..4127440c0c 100644\n--- a/target/i386/whpx/whpx-all.c\n+++ b/target/i386/whpx/whpx-all.c\n@@ -1082,6 +1082,8 @@ HRESULT whpx_set_exception_exit_bitmap(UINT64 exceptions)\n /* Register for MSR and CPUID exits */\n memset(&prop, 0, sizeof(WHV_PARTITION_PROPERTY));\n prop.ExtendedVmExits.X64MsrExit = 1;\n+ prop.ExtendedVmExits.X64CpuidExit = 1;\n+\n if (exceptions != 0) {\n prop.ExtendedVmExits.ExceptionExit = 1;\n }\n@@ -1898,6 +1900,18 @@ int whpx_vcpu_run(CPUState *cpu)\n WHV_REGISTER_NAME reg_names[3];\n UINT32 reg_count;\n bool is_known_msr = 0; \n+ uint64_t val;\n+\n+ if (vcpu->exit_ctx.MsrAccess.AccessInfo.IsWrite) {\n+ val = ((uint32_t)vcpu->exit_ctx.MsrAccess.Rax) |\n+ ((uint64_t)(vcpu->exit_ctx.MsrAccess.Rdx) << 32);\n+ } else {\n+ /*\n+ * Workaround for [-Werror=maybe-uninitialized]\n+ * with GCC. Not needed with Clang.\n+ */\n+ val = 0;\n+ }\n \n reg_names[0] = WHvX64RegisterRip;\n reg_names[1] = WHvX64RegisterRax;\n@@ -1911,7 +1925,47 @@ int whpx_vcpu_run(CPUState *cpu)\n && !vcpu->exit_ctx.MsrAccess.AccessInfo.IsWrite\n && !whpx_irqchip_in_kernel()) {\n is_known_msr = 1;\n- reg_values[1].Reg32 = (uint32_t)X86_CPU(cpu)->env.apic_bus_freq;\n+ val = X86_CPU(cpu)->env.apic_bus_freq;\n+ }\n+\n+ if (!whpx_irqchip_in_kernel() &&\n+ vcpu->exit_ctx.MsrAccess.MsrNumber == MSR_IA32_APICBASE) {\n+ is_known_msr = 1;\n+ if (!vcpu->exit_ctx.MsrAccess.AccessInfo.IsWrite) {\n+ /* Read path unreachable on Hyper-V */\n+ abort();\n+ } else {\n+ WHV_REGISTER_VALUE reg = {.Reg64 = val};\n+ int msr_ret = cpu_set_apic_base(X86_CPU(cpu)->apic_state, val);\n+ if (msr_ret < 0) {\n+ x86_emul_raise_exception(&X86_CPU(cpu)->env, EXCP0D_GPF, 0);\n+ }\n+ whpx_set_reg(cpu, WHvX64RegisterApicBase, reg);\n+ }\n+ }\n+\n+ if (!whpx_irqchip_in_kernel() &&\n+ vcpu->exit_ctx.MsrAccess.MsrNumber >= MSR_APIC_START &&\n+ vcpu->exit_ctx.MsrAccess.MsrNumber <= MSR_APIC_END) {\n+ int index = vcpu->exit_ctx.MsrAccess.MsrNumber - MSR_APIC_START;\n+ int msr_ret;\n+ is_known_msr = 1;\n+ if (!vcpu->exit_ctx.MsrAccess.AccessInfo.IsWrite) {\n+ bql_lock();\n+ msr_ret = apic_msr_read(X86_CPU(cpu)->apic_state, index, &val);\n+ bql_unlock();\n+ reg_values[1].Reg64 = val;\n+ if (msr_ret < 0) {\n+ x86_emul_raise_exception(&X86_CPU(cpu)->env, EXCP0D_GPF, 0);\n+ }\n+ } else {\n+ bql_lock();\n+ msr_ret = apic_msr_write(X86_CPU(cpu)->apic_state, index, val);\n+ bql_unlock();\n+ if (msr_ret < 0) {\n+ x86_emul_raise_exception(&X86_CPU(cpu)->env, EXCP0D_GPF, 0);\n+ }\n+ }\n }\n /*\n * For all unsupported MSR access we:\n@@ -1921,6 +1975,11 @@ int whpx_vcpu_run(CPUState *cpu)\n reg_count = vcpu->exit_ctx.MsrAccess.AccessInfo.IsWrite ?\n 1 : 3;\n \n+ if (!vcpu->exit_ctx.MsrAccess.AccessInfo.IsWrite) {\n+ reg_values[1].Reg32 = (uint32_t)val;\n+ reg_values[2].Reg32 = (uint32_t)(val >> 32);\n+ }\n+\n if (!is_known_msr) {\n trace_whpx_unsupported_msr_access(vcpu->exit_ctx.MsrAccess.MsrNumber,\n vcpu->exit_ctx.MsrAccess.AccessInfo.IsWrite);\n@@ -1939,6 +1998,47 @@ int whpx_vcpu_run(CPUState *cpu)\n ret = 0;\n break;\n }\n+ case WHvRunVpExitReasonX64Cpuid: {\n+ WHV_REGISTER_VALUE reg_values[5] = {0};\n+ WHV_REGISTER_NAME reg_names[5];\n+ UINT32 reg_count = 5;\n+ X86CPU *x86_cpu = X86_CPU(cpu);\n+ CPUX86State *env = &x86_cpu->env;\n+\n+ reg_names[0] = WHvX64RegisterRip;\n+ reg_names[1] = WHvX64RegisterRax;\n+ reg_names[2] = WHvX64RegisterRcx;\n+ reg_names[3] = WHvX64RegisterRdx;\n+ reg_names[4] = WHvX64RegisterRbx;\n+\n+ reg_values[0].Reg64 =\n+ vcpu->exit_ctx.VpContext.Rip +\n+ vcpu->exit_ctx.VpContext.InstructionLength;\n+\n+ reg_values[1].Reg64 = vcpu->exit_ctx.CpuidAccess.DefaultResultRax;\n+ reg_values[2].Reg64 = vcpu->exit_ctx.CpuidAccess.DefaultResultRcx;\n+ reg_values[3].Reg64 = vcpu->exit_ctx.CpuidAccess.DefaultResultRdx;\n+ reg_values[4].Reg64 = vcpu->exit_ctx.CpuidAccess.DefaultResultRbx;\n+\n+ if (vcpu->exit_ctx.CpuidAccess.Rax == 1) {\n+ if (cpu_has_x2apic_feature(env)) {\n+ reg_values[2].Reg64 |= CPUID_EXT_X2APIC;\n+ }\n+ }\n+\n+ hr = whp_dispatch.WHvSetVirtualProcessorRegisters(\n+ whpx->partition,\n+ cpu->cpu_index,\n+ reg_names, reg_count,\n+ reg_values);\n+\n+ if (FAILED(hr)) {\n+ error_report(\"WHPX: Failed to set CpuidAccess state \"\n+ \" registers, hr=%08lx\", hr);\n+ }\n+ ret = 0;\n+ break;\n+ }\n case WHvRunVpExitReasonException:\n whpx_get_registers(cpu, WHPX_LEVEL_FULL_STATE);\n \n@@ -2136,6 +2236,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms)\n WHV_PROCESSOR_FEATURES_BANKS processor_features;\n WHV_PROCESSOR_PERFMON_FEATURES perfmon_features;\n bool is_legacy_os = false;\n+ UINT32 cpuidExitList[] = {1};\n \n whpx = &whpx_global;\n \n@@ -2354,6 +2455,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms)\n /* Register for MSR and CPUID exits */\n memset(&prop, 0, sizeof(WHV_PARTITION_PROPERTY));\n prop.ExtendedVmExits.X64MsrExit = 1;\n+ prop.ExtendedVmExits.X64CpuidExit = 1;\n \n hr = whp_dispatch.WHvSetPartitionProperty(\n whpx->partition,\n@@ -2366,6 +2468,36 @@ int whpx_accel_init(AccelState *as, MachineState *ms)\n goto error;\n }\n \n+ memset(&prop, 0, sizeof(WHV_PARTITION_PROPERTY));\n+ prop.X64MsrExitBitmap.UnhandledMsrs = 1;\n+ if (!whpx_irqchip_in_kernel()) {\n+ prop.X64MsrExitBitmap.ApicBaseMsrWrite = 1;\n+ }\n+\n+ hr = whp_dispatch.WHvSetPartitionProperty(\n+ whpx->partition,\n+ WHvPartitionPropertyCodeX64MsrExitBitmap,\n+ &prop,\n+ sizeof(WHV_PARTITION_PROPERTY));\n+ if (FAILED(hr)) {\n+ error_report(\"WHPX: Failed to set MSR exit bitmap, hr=%08lx\", hr);\n+ ret = -EINVAL;\n+ goto error;\n+ }\n+\n+ hr = whp_dispatch.WHvSetPartitionProperty(\n+ whpx->partition,\n+ WHvPartitionPropertyCodeCpuidExitList,\n+ cpuidExitList,\n+ RTL_NUMBER_OF(cpuidExitList) * sizeof(UINT32));\n+\n+ if (FAILED(hr)) {\n+ error_report(\"WHPX: Failed to set partition CpuidExitList hr=%08lx\",\n+ hr);\n+ ret = -EINVAL;\n+ goto error;\n+ }\n+\n /*\n * We do not want to intercept any exceptions from the guest,\n * until we actually start debugging with gdb.\n","prefixes":["v6","02/11"]}