{"id":2219670,"url":"http://patchwork.ozlabs.org/api/patches/2219670/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260403162541.86608-8-sgdfkk@163.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260403162541.86608-8-sgdfkk@163.com>","list_archive_url":null,"date":"2026-04-03T16:25:41","name":"[v7,7/7] mips: loongson: ls1c300 dts and bindings","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"f34dcce5458551f6a9e4152d781d23ab8d79d543","submitter":{"id":92844,"url":"http://patchwork.ozlabs.org/api/people/92844/?format=json","name":null,"email":"sgdfkk@163.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260403162541.86608-8-sgdfkk@163.com/mbox/","series":[{"id":498655,"url":"http://patchwork.ozlabs.org/api/series/498655/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=498655","date":"2026-04-03T16:25:35","name":"add loongson mips ls1c300 initial support","version":7,"mbox":"http://patchwork.ozlabs.org/series/498655/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2219670/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2219670/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=163.com header.i=@163.com header.a=rsa-sha256\n header.s=s110527 header.b=ibXwqdvE;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)","phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=163.com","phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de","phobos.denx.de;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=163.com header.i=@163.com header.b=\"ibXwqdvE\";\n\tdkim-atps=neutral","phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=163.com","phobos.denx.de; spf=pass smtp.mailfrom=sgdfkk@163.com"],"Received":["from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fnPJ5385pz1xtJ\n\tfor ; Sat, 04 Apr 2026 03:27:01 +1100 (AEDT)","from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id EF90B84181;\n\tFri, 3 Apr 2026 18:26:06 +0200 (CEST)","by phobos.denx.de (Postfix, from userid 109)\n id 8804D84105; Fri, 3 Apr 2026 18:25:56 +0200 (CEST)","from m16.mail.163.com (m16.mail.163.com [117.135.210.2])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 608E884118\n for ; Fri, 3 Apr 2026 18:25:52 +0200 (CEST)","from server-e.. (unknown [])\n by gzsmtp3 (Coremail) with SMTP id PigvCgAnAXQF6s9pHqSgBw--.137S9;\n Sat, 04 Apr 2026 00:25:49 +0800 (CST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,HK_RANDOM_ENVFROM,\n HK_RANDOM_FROM,RCVD_IN_DNSWL_BLOCKED,\n RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED,\n SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY autolearn=no\n autolearn_force=no version=3.4.2","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com;\n s=s110527; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=of\n 5OShH0/01X2M4+qgw1fbWooJ6uzl9sPzdbS4gX1rU=; b=ibXwqdvE6fQWdzB8fm\n 3z6QmoXMJpDua2owVimLCeA51AUHGfpaea3nNovLCCOsTbnSzGrNTmWmNomZ66bn\n G1qWM8AvOKKkF4S52DFov2evBBuOY2CrlXYu7mI0zVySWHii6Ie8ZohhNWxeAOH4\n YMokEEuBx9tVTRduA8xs92AyQ=","From":"sgdfkk@163.com","To":"u-boot@lists.denx.de","Cc":"Du Huanpeng ","Subject":"[PATCH v7 7/7] mips: loongson: ls1c300 dts and bindings","Date":"Sat, 4 Apr 2026 00:25:41 +0800","Message-ID":"<20260403162541.86608-8-sgdfkk@163.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260403162541.86608-1-sgdfkk@163.com>","References":"<20260403162541.86608-1-sgdfkk@163.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-CM-TRANSID":"PigvCgAnAXQF6s9pHqSgBw--.137S9","X-Coremail-Antispam":"1Uf129KBjvJXoW3AF1UZr17urW7Cr45Gr15Arb_yoWxCF1Upw\n 1qkFZ5tr40vF129w1F9a48JF1fJFW0kFy7J3ZFqFy8Cw13KFWjyF1fKaySqFy3Xr48Z3yx\n XFZrX34jvFsFvw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2\n 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07Um4E_UUUUU=","X-Originating-IP":"[240e:3b0:4805:581::3001]","X-CM-SenderInfo":"xvjgwyrn6rljoofrz/xtbC5w0MY2nP6g28pgAA3e","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"From: Du Huanpeng \n\n- ls1c300 dtsi\n- ls1c300-eval board dts\n- clk binding header\n- reset binding header\n\nSigned-off-by: Du Huanpeng \n---\n arch/mips/dts/loongson32-ls1c300b.dtsi | 151 ++++++++++++++++++++++\n arch/mips/dts/ls1c300-eval.dts | 30 +++++\n include/dt-bindings/clock/ls1c300-clk.h | 18 +++\n include/dt-bindings/reset/ls1c300-reset.h | 36 ++++++\n 4 files changed, 235 insertions(+)\n create mode 100644 arch/mips/dts/loongson32-ls1c300b.dtsi\n create mode 100644 arch/mips/dts/ls1c300-eval.dts\n create mode 100644 include/dt-bindings/clock/ls1c300-clk.h\n create mode 100644 include/dt-bindings/reset/ls1c300-reset.h","diff":"diff --git a/arch/mips/dts/loongson32-ls1c300b.dtsi b/arch/mips/dts/loongson32-ls1c300b.dtsi\nnew file mode 100644\nindex 00000000000..26b0c707459\n--- /dev/null\n+++ b/arch/mips/dts/loongson32-ls1c300b.dtsi\n@@ -0,0 +1,151 @@\n+// SPDX-License-Identifier: GPL-2.0\n+#include \n+#include \n+\n+/ {\n+\t#address-cells = <1>;\n+\t#size-cells = <1>;\n+\tcompatible = \"loongson,ls1c300-soc\";\n+\n+\tcpus {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tcpu@0 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\treg = <0>;\n+\t\t\tcompatible = \"loongson,gs232\", \"mips,mips4Kc\";\n+\t\t\tclocks = <&acc CLK_CPU_THROT>;\n+\t\t};\n+\t};\n+\n+\tclocks {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tbootph-all;\n+\n+\n+\t\txtal: oscillator {\n+\t\t\tcompatible = \"fixed-clock\";\n+\t\t\tclock-frequency = <24000000>;\n+\t\t\t#clock-cells = <0>;\n+\t\t};\n+\t};\n+\n+\tsoc {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tcompatible = \"simple-bus\";\n+\t\tranges;\n+\n+\t\tacc: clock-controller@1fe78030 {\n+\t\t\tcompatible = \"loongson,ls1c300-clk\";\n+\t\t\tclocks = <&xtal>;\n+\t\t\t#clock-cells = <1>;\n+\t\t\treg = <0x1fe78030 0x8>, <0x1fe7c010 0x4>;\n+\t\t\tbootph-all;\n+\t\t};\n+\n+\t\tuart0: serial@1fe40000 {\n+\t\t\tcompatible = \"loongson,ls1c300-uart\", \"ns16550a\";\n+\t\t\tclocks = <&acc CLK_APB>;\n+\t\t\treg = <0x1fe40000 0x100>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tuart1: serial@1fe44000 {\n+\t\t\tcompatible = \"loongson,ls1c300-uart\", \"ns16550a\";\n+\t\t\tclocks = <&acc CLK_APB>;\n+\t\t\treg = <0x1fe44000 0x100>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tuart2: serial@1fe48000 {\n+\t\t\tcompatible = \"loongson,ls1c300-uart\", \"ns16550a\";\n+\t\t\tclocks = <&acc CLK_APB>;\n+\t\t\treg = <0x1fe48000 0x100>;\n+\t\t\tresets = <&shut_ctrl UART2_SHUT>;\n+\t\t\treset-names = \"uart2\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tuart3: serial@1fe4c000 {\n+\t\t\tcompatible = \"loongson,ls1c300-uart\", \"ns16550a\";\n+\t\t\tclocks = <&acc CLK_APB>;\n+\t\t\treg = <0x1fe4c000 0x100>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tuart4: serial@1fe4c400 {\n+\t\t\tcompatible = \"loongson,ls1c300-uart\", \"ns16550a\";\n+\t\t\tclocks = <&acc CLK_APB>;\n+\t\t\treg = <0x1fe4c400 0x100>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tuart5: serial@1fe4c500 {\n+\t\t\tcompatible = \"loongson,ls1c300-uart\", \"ns16550a\";\n+\t\t\tclocks = <&acc CLK_APB>;\n+\t\t\treg = <0x1fe4c500 0x100>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tuart6: serial@1fe4c600 {\n+\t\t\tcompatible = \"loongson,ls1c300-uart\", \"ns16550a\";\n+\t\t\tclocks = <&acc CLK_APB>;\n+\t\t\treg = <0x1fe4c600 0x100>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tuart7: serial@1fe4c700 {\n+\t\t\tcompatible = \"loongson,ls1c300-uart\", \"ns16550a\";\n+\t\t\tclocks = <&acc CLK_APB>;\n+\t\t\treg = <0x1fe4c700 0x100>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tuart8: serial@1fe4c800 {\n+\t\t\tcompatible = \"loongson,ls1c300-uart\", \"ns16550a\";\n+\t\t\tclocks = <&acc CLK_APB>;\n+\t\t\treg = <0x1fe4c800 0x100>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tuart9: serial@1fe4c900 {\n+\t\t\tcompatible = \"loongson,ls1c300-uart\", \"ns16550a\";\n+\t\t\tclocks = <&acc CLK_APB>;\n+\t\t\treg = <0x1fe4c900 0x100>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tuart10: serial@1fe4ca00 {\n+\t\t\tcompatible = \"loongson,ls1c300-uart\", \"ns16550a\";\n+\t\t\tclocks = <&acc CLK_APB>;\n+\t\t\treg = <0x1fe4ca00 0x100>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tuart11: serial@1fe4cb00 {\n+\t\t\tcompatible = \"loongson,ls1c300-uart\", \"ns16550a\";\n+\t\t\tclocks = <&acc CLK_APB>;\n+\t\t\treg = <0x1fe4cb00 0x100>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\twdt: watchdog@1fe5c060 {\n+\t\t\tcompatible = \"loongson,ls1c300-wdt\";\n+\t\t\tclocks = <&acc CLK_APB>;\n+\t\t\treg = <0x1fe5c060 0x10>;\n+\t\t};\n+\n+\t\treset-controller {\n+\t\t\tcompatible = \"wdt-reboot\";\n+\t\t\twdt = <&wdt>;\n+\t\t};\n+\n+\t\tshut_ctrl: reset-controller@1fd00420 {\n+\t\t\tcompatible = \"loongson,shut_ctrl\";\n+\t\t\treg = <0x1fd00420 0x4>;\n+\t\t\t#reset-cells = <1>;\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/mips/dts/ls1c300-eval.dts b/arch/mips/dts/ls1c300-eval.dts\nnew file mode 100644\nindex 00000000000..cc3c267a5bf\n--- /dev/null\n+++ b/arch/mips/dts/ls1c300-eval.dts\n@@ -0,0 +1,30 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (C) 2022 Du Huanpeng \n+ */\n+\n+/dts-v1/;\n+\n+#include \"loongson32-ls1c300b.dtsi\"\n+\n+/ {\n+\tcompatible = \"lsmips,ls1c300-soc\";\n+\tmodel = \"ls1c300-eval\";\n+\n+\taliases {\n+\t\tserial0 = &uart2;\n+\t};\n+\n+\tmemory@80000000 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x80000000 0x4000000>;\n+\t};\n+\n+\tchosen {\n+\t\tstdout-path = \"serial0:115200n8\";\n+\t};\n+};\n+\n+&uart2 {\n+\tstatus = \"okay\";\n+};\ndiff --git a/include/dt-bindings/clock/ls1c300-clk.h b/include/dt-bindings/clock/ls1c300-clk.h\nnew file mode 100644\nindex 00000000000..170728693be\n--- /dev/null\n+++ b/include/dt-bindings/clock/ls1c300-clk.h\n@@ -0,0 +1,18 @@\n+/* SPDX-License-Identifier: GPL-2.0-only */\n+/*\n+ * Copyright (C) 2022 Du Huanpeng \n+ */\n+\n+#ifndef __DT_BINDINGS_LS1C300_CLK_H__\n+#define __DT_BINDINGS_LS1C300_CLK_H__\n+\n+#define CLK_XTAL\t0\n+#define CLK_PLL\t\t1\n+#define CLK_CPU\t\t2\n+#define CLK_APB\t\t3\n+#define CLK_CAMERA\t4\n+#define CLK_PIX\t\t5\n+#define CLK_AXIMUX\t6\n+#define CLK_CPU_THROT\t7\n+\n+#endif /* __DT_BINDINGS_LS1C300_CLK_H__ */\ndiff --git a/include/dt-bindings/reset/ls1c300-reset.h b/include/dt-bindings/reset/ls1c300-reset.h\nnew file mode 100644\nindex 00000000000..44734ee50a9\n--- /dev/null\n+++ b/include/dt-bindings/reset/ls1c300-reset.h\n@@ -0,0 +1,36 @@\n+/* SPDX-License-Identifier: GPL-2.0-only */\n+/*\n+ * Copyright (C) 2022 Du Huanpeng \n+ */\n+\n+#ifndef _DT_BINDINGS_LS1C300_RESET_H_\n+#define _DT_BINDINGS_LS1C300_RESET_H_\n+\n+#define ADC_SHUT 25\n+#define SDIO_SHUT 24\n+#define DMA2_SHUT 23\n+#define DMA1_SHUT 22\n+#define DMA0_SHUT 21\n+#define SPI1_SHUT 20\n+#define SPI0_SHUT 19\n+#define I2C2_SHUT 18\n+#define I2C1_SHUT 17\n+#define I2C0_SHUT 16\n+#define AC97_SHUT 15\n+#define I2S_SHUT 14\n+#define UART3_SHUT 13\n+#define UART2_SHUT 12\n+#define UART1_SHUT 11\n+#define UART0_SHUT 10\n+#define CAN1_SHUT 9\n+#define CAN0_SHUT 8\n+#define ECC_SHUT 7\n+#define MAC_SHUT 6\n+#define USBHOST_SHUT 5\n+#define USBOTG_SHUT 4\n+#define SDRAM_SHUT 3\n+#define SRAM_SHUT 2\n+#define CAM_SHUT 1\n+#define LCD_SHUT 0\n+\n+#endif /* _DT_BINDINGS_LS1C300_RESET_H_*/\n","prefixes":["v7","7/7"]}