{"id":2219667,"url":"http://patchwork.ozlabs.org/api/patches/2219667/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260403162541.86608-4-sgdfkk@163.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260403162541.86608-4-sgdfkk@163.com>","list_archive_url":null,"date":"2026-04-03T16:25:37","name":"[v7,3/7] mips: loongson: lowlevel debug serial","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"1c9869cc8bf39b1815212be1e651447e26c40dca","submitter":{"id":92844,"url":"http://patchwork.ozlabs.org/api/people/92844/?format=json","name":null,"email":"sgdfkk@163.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260403162541.86608-4-sgdfkk@163.com/mbox/","series":[{"id":498655,"url":"http://patchwork.ozlabs.org/api/series/498655/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=498655","date":"2026-04-03T16:25:35","name":"add loongson mips ls1c300 initial support","version":7,"mbox":"http://patchwork.ozlabs.org/series/498655/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2219667/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2219667/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=163.com header.i=@163.com header.a=rsa-sha256\n header.s=s110527 header.b=Jar2xi9W;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)","phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=163.com","phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de","phobos.denx.de;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=163.com header.i=@163.com header.b=\"Jar2xi9W\";\n\tdkim-atps=neutral","phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=163.com","phobos.denx.de; spf=pass smtp.mailfrom=sgdfkk@163.com"],"Received":["from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fnPHZ3pSxz1xtJ\n\tfor ; Sat, 04 Apr 2026 03:26:34 +1100 (AEDT)","from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 354178416F;\n\tFri, 3 Apr 2026 18:25:58 +0200 (CEST)","by phobos.denx.de (Postfix, from userid 109)\n id DEF1984148; Fri, 3 Apr 2026 18:25:55 +0200 (CEST)","from m16.mail.163.com (m16.mail.163.com [117.135.210.4])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 3DDF6840F1\n for ; Fri, 3 Apr 2026 18:25:51 +0200 (CEST)","from server-e.. (unknown [])\n by gzsmtp3 (Coremail) with SMTP id PigvCgAnAXQF6s9pHqSgBw--.137S5;\n Sat, 04 Apr 2026 00:25:48 +0800 (CST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,HK_RANDOM_ENVFROM,\n HK_RANDOM_FROM,RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,\n RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED,\n SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY autolearn=no\n autolearn_force=no version=3.4.2","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com;\n s=s110527; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=+R\n RctQiDz10VO7hYlJBBD3FZic+A0WGqjtUyOAGP5Sw=; b=Jar2xi9WREcy4dZv3J\n 8ZDMS7AwYohT4/n+hPgmKhGU+v3JIV2kI4XbpdpXEmC+uoR0WGNE3If1Q9cxqgYU\n W3RF3WBCnyOX2D3LWltuSH0j3uadeOWV/XagcfnwkriDxOue4OE+Ln75m3FiX13N\n 8cucAC7GPIzXPAJQhsyEobS/s=","From":"sgdfkk@163.com","To":"u-boot@lists.denx.de","Cc":"Du Huanpeng ","Subject":"[PATCH v7 3/7] mips: loongson: lowlevel debug serial","Date":"Sat, 4 Apr 2026 00:25:37 +0800","Message-ID":"<20260403162541.86608-4-sgdfkk@163.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260403162541.86608-1-sgdfkk@163.com>","References":"<20260403162541.86608-1-sgdfkk@163.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-CM-TRANSID":"PigvCgAnAXQF6s9pHqSgBw--.137S5","X-Coremail-Antispam":"1Uf129KBjvJXoWxtw1UZrWrCw1fJr4kGFy3urg_yoW7XFy7pF\n 1xAan5KF4DXw47KasYy3WkGrnxtrs5Jry7JFnrXF1ru3Z7t3Z5CF42kFn0vrW3JFZ5GrWF\n 9ayavrW2gas7Zw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2\n 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07j0yIUUUUUU=","X-Originating-IP":"[240e:3b0:4805:581::3001]","X-CM-SenderInfo":"xvjgwyrn6rljoofrz/xtbC5wwMY2nP6gy8aQAA3R","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"From: Du Huanpeng \n\nset pin to uart alternate function and enable uart for lowlevel debug,\nalso future pinctrl driver can base on this code.\n\nSigned-off-by: Du Huanpeng \n---\n arch/mips/mach-loongson/include/mach/serial.h | 16 +++\n arch/mips/mach-loongson/ls1c300/gpio.c | 66 +++++++++++\n arch/mips/mach-loongson/ls1c300/serial.c | 104 ++++++++++++++++++\n 3 files changed, 186 insertions(+)\n create mode 100644 arch/mips/mach-loongson/include/mach/serial.h\n create mode 100644 arch/mips/mach-loongson/ls1c300/gpio.c\n create mode 100644 arch/mips/mach-loongson/ls1c300/serial.c","diff":"diff --git a/arch/mips/mach-loongson/include/mach/serial.h b/arch/mips/mach-loongson/include/mach/serial.h\nnew file mode 100644\nindex 00000000000..7afe5788cb7\n--- /dev/null\n+++ b/arch/mips/mach-loongson/include/mach/serial.h\n@@ -0,0 +1,16 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 MediaTek Inc.\n+ *\n+ * Author: Gao Weijie \n+ *\n+ * Copyright (C) 2022 Du Huanpeng \n+ */\n+\n+#ifndef __LSMIPS_SERIAL_H_\n+#define __LSMIPS_SERIAL_H_\n+\n+void loongson_spl_serial_init(void);\n+int gpio_set_alternate(int gpio, int func);\n+\n+#endif /* __LSMIPS_SERIAL_H_ */\ndiff --git a/arch/mips/mach-loongson/ls1c300/gpio.c b/arch/mips/mach-loongson/ls1c300/gpio.c\nnew file mode 100644\nindex 00000000000..7f160408382\n--- /dev/null\n+++ b/arch/mips/mach-loongson/ls1c300/gpio.c\n@@ -0,0 +1,66 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright (C) 2022 Du Huanpeng \n+ */\n+\n+#include \n+#include \n+\n+#define CBUS_FIRST0\t0xbfd011c0\n+#define CBUS_SECOND0\t0xbfd011d0\n+#define CBUS_THIRD0\t0xbfd011e0\n+#define CBUS_FOURTHT0\t0xbfd011f0\n+#define CBUS_FIFTHT0\t0xbfd01200\n+\n+#define CBUS_FIRST1\t0xbfd011c4\n+#define CBUS_SECOND1\t0xbfd011d4\n+#define CBUS_THIRD1\t0xbfd011e4\n+#define CBUS_FOURTHT1\t0xbfd011f4\n+#define CBUS_FIFTHT1\t0xbfd01204\n+\n+#define CBUS_FIRST2\t0xbfd011c8\n+#define CBUS_SECOND2\t0xbfd011d8\n+#define CBUS_THIRD2\t0xbfd011e8\n+#define CBUS_FOURTHT2\t0xbfd011f8\n+#define CBUS_FIFTHT2\t0xbfd01208\n+\n+#define CBUS_FIRST3\t0xbfd011cc\n+#define CBUS_SECOND3\t0xbfd011dc\n+#define CBUS_THIRD3\t0xbfd011ec\n+#define CBUS_FOURTHT3\t0xbfd011fc\n+#define CBUS_FIFTHT3\t0xbfd0120c\n+\n+/*\n+ * pinmux for debug uart and spl only, for others, please\n+ * use a pinctrl driver and device-tree for pin muxing.\n+ *\n+ * @gpio: gpio number\n+ * @func: alternate function 1 to 5, 0 for GPIO.\n+ */\n+\n+int gpio_set_alternate(int gpio, int func)\n+{\n+\tvolatile void __iomem *addr;\n+\tint i;\n+\n+\tif (gpio < 0 || gpio > 104)\n+\t\treturn -ENODEV;\n+\tif (func < 0 || func > 5)\n+\t\treturn -EINVAL;\n+\n+\tif (func) {\n+\t\ti = func - 1;\n+\t\taddr = (void *)CBUS_FIRST0 + i * 16;\n+\t\tset_bit(gpio, addr);\n+\t} else {\n+\t\t/* GPIO, clear CBUS 1 ~ 5 */\n+\t\ti = 5;\n+\t}\n+\n+\twhile (i--) {\n+\t\taddr = (void *)CBUS_FIRST0 + 16 * i;\n+\t\tclear_bit(gpio, addr);\n+\t}\n+\n+\treturn 0;\n+}\ndiff --git a/arch/mips/mach-loongson/ls1c300/serial.c b/arch/mips/mach-loongson/ls1c300/serial.c\nnew file mode 100644\nindex 00000000000..a7697574dad\n--- /dev/null\n+++ b/arch/mips/mach-loongson/ls1c300/serial.c\n@@ -0,0 +1,104 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (C) 2020-2026 Du Huanpeng \n+ */\n+\n+#include \n+#include \n+\n+struct uart_pin_config {\n+\tchar port;\n+\tchar afunc;\n+\tchar rx;\n+\tchar tx;\n+};\n+\n+struct uart_pin_config con[] = {\n+#if CONFIG_CONS_INDEX == 0\n+\t{ 0, 2, 74, 75 },\n+\t{ 0, 3, 23, 24 },\n+\t{ 0, 3, 99, 100 },\n+\n+#elif CONFIG_CONS_INDEX == 1\n+\t{ 1, 1, 17, 18 },\n+\t{ 1, 1, 101, 102 },\n+\t{ 1, 2, 40, 41 },\n+\t{ 1, 4, 2, 3 },\n+\n+#elif CONFIG_CONS_INDEX == 2\n+\t{ 2, 2, 36, 37 },\n+\t{ 2, 2, 42, 43 },\n+\t{ 2, 3, 27, 28 },\n+\t{ 2, 3, 103, 104 },\n+\t{ 2, 4, 4, 5 },\n+\n+#elif CONFIG_CONS_INDEX == 3\n+\t{ 3, 2, 17, 18 },\n+\t{ 3, 2, 33, 34 },\n+\t{ 3, 2, 44, 45 },\n+\t{ 3, 4, 0, 1 },\n+\n+#elif CONFIG_CONS_INDEX == 4\n+\t{ 4, 5, 23, 24 },\n+\t{ 4, 5, 58, 59 },\n+\t{ 4, 5, 80, 79 },\n+\n+#elif CONFIG_CONS_INDEX == 5\n+\t{ 5, 5, 25, 26 },\n+\t{ 5, 5, 60, 61 },\n+\t{ 5, 5, 81, 78 },\n+\n+#elif CONFIG_CONS_INDEX == 6\n+\t{ 6, 5, 27, 46 },\n+\t{ 6, 5, 62, 63 },\n+\n+#elif CONFIG_CONS_INDEX == 7\n+\t{ 7, 5, 57, 56 },\n+\t{ 7, 5, 64, 65 },\n+\t{ 7, 5, 87, 88 },\n+\n+#elif CONFIG_CONS_INDEX == 8\n+\t{ 8, 5, 55, 54 },\n+\t{ 8, 5, 66, 67 },\n+\t{ 8, 5, 89, 90 },\n+\n+#elif CONFIG_CONS_INDEX == 9\n+\t{ 9, 5, 53, 52 },\n+\t{ 9, 5, 68, 69 },\n+\t{ 9, 5, 85, 86 },\n+\n+#elif CONFIG_CONS_INDEX == 10\n+\t{ 10, 5, 51, 50 },\n+\t{ 10, 5, 70, 71 },\n+\t{ 10, 5, 84, 82 },\n+\n+#elif CONFIG_CONS_INDEX == 11\n+\t{ 11, 5, 49, 48 },\n+\t{ 11, 5, 72, 73 },\n+#endif /* CONFIG_CONS_INDEX */\n+};\n+\n+#define UART2_RX\t36\n+#define UART2_TX\t37\n+#define AFUNC\t\t2\n+\n+void loongson_spl_serial_init(void)\n+{\n+#if defined(CONFIG_SPL_SERIAL)\n+\tint pin_rx, pin_tx;\n+\tint afunc;\n+\n+\tif (CONFIG_CONS_PIN < ARRAY_SIZE(con)) {\n+\t\tpin_rx = con[CONFIG_CONS_PIN].rx;\n+\t\tpin_tx = con[CONFIG_CONS_PIN].tx;\n+\t\tafunc = con[CONFIG_CONS_PIN].afunc;\n+\t} else {\n+\t\tpin_rx = UART2_RX;\n+\t\tpin_tx = UART2_TX;\n+\t\tafunc = AFUNC;\n+\t}\n+\n+\tgpio_set_alternate(pin_rx, afunc);\n+\tgpio_set_alternate(pin_tx, afunc);\n+#endif /* CONFIG_SPL_SERIAL */\n+}\n","prefixes":["v7","3/7"]}