{"id":2219643,"url":"http://patchwork.ozlabs.org/api/patches/2219643/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-mtd/patch/20260403-winbond-v6-18-rc1-spi-nor-swp-v4-13-833dab5e7288@bootlin.com/","project":{"id":3,"url":"http://patchwork.ozlabs.org/api/projects/3/?format=json","name":"Linux MTD development","link_name":"linux-mtd","list_id":"linux-mtd.lists.infradead.org","list_email":"linux-mtd@lists.infradead.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260403-winbond-v6-18-rc1-spi-nor-swp-v4-13-833dab5e7288@bootlin.com>","list_archive_url":null,"date":"2026-04-03T16:09:31","name":"[v4,13/27] mtd: spi-nor: swp: Create helpers for building the SR register","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"2f0919d680a669814d7470faab147f7ef82a331a","submitter":{"id":73368,"url":"http://patchwork.ozlabs.org/api/people/73368/?format=json","name":"Miquel Raynal","email":"miquel.raynal@bootlin.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-mtd/patch/20260403-winbond-v6-18-rc1-spi-nor-swp-v4-13-833dab5e7288@bootlin.com/mbox/","series":[{"id":498652,"url":"http://patchwork.ozlabs.org/api/series/498652/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-mtd/list/?series=498652","date":"2026-04-03T16:09:18","name":"mtd: spi-nor: Enhance software protection","version":4,"mbox":"http://patchwork.ozlabs.org/series/498652/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2219643/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2219643/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=lists.infradead.org header.i=@lists.infradead.org\n header.a=rsa-sha256 header.s=bombadil.20210309 header.b=IPagMqsK;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n secure) header.d=infradead.org header.i=@infradead.org header.a=rsa-sha256\n header.s=casper.20170209 header.b=KEnwPFjK;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=bootlin.com header.i=@bootlin.com header.a=rsa-sha256\n header.s=dkim header.b=LUXasgoY;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=none (no SPF record) smtp.mailfrom=lists.infradead.org\n (client-ip=2607:7c80:54:3::133; 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See\n https://knowledge.validity.com/hc/en-us/articles/20961730681243\n for more information.\n [185.171.202.116 listed in\n bl.score.senderscore.com]","X-BeenThere":"linux-mtd@lists.infradead.org","X-Mailman-Version":"2.1.34","Precedence":"list","List-Id":"Linux MTD discussion mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-mtd\" ","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"},"content":"The status register contains 3 or 4 BP (Block Protect) bits, 0 or 1\nTB (Top/Bottom) bit, soon 0 or 1 CMP (Complement) bit. The last BP bit\nand the TB bit locations change between vendors. The whole logic of\nbuildling the content of the status register based on some input\nconditions is used two times and soon will be used 4 times.\n\nCreate dedicated helpers for these steps.\n\nSigned-off-by: Miquel Raynal \n---\n drivers/mtd/spi-nor/swp.c | 83 +++++++++++++++++++++++++++++------------------\n 1 file changed, 51 insertions(+), 32 deletions(-)","diff":"diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c\nindex f068cb9c8f6d..e2e423b20989 100644\n--- a/drivers/mtd/spi-nor/swp.c\n+++ b/drivers/mtd/spi-nor/swp.c\n@@ -123,6 +123,43 @@ static bool spi_nor_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, u64 len,\n \treturn spi_nor_check_lock_status_sr(nor, ofs, len, sr, false);\n }\n \n+static int spi_nor_sr_set_bp_mask(struct spi_nor *nor, u8 *sr, u8 pow)\n+{\n+\tu8 mask = spi_nor_get_sr_bp_mask(nor);\n+\tu8 val = pow << SR_BP_SHIFT;\n+\n+\tif (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3)\n+\t\tval = (val & ~SR_BP3) | SR_BP3_BIT6;\n+\n+\tif (val & ~mask)\n+\t\treturn -EINVAL;\n+\n+\tsr[0] = val;\n+\n+\treturn 0;\n+}\n+\n+static int spi_nor_build_sr(struct spi_nor *nor, const u8 *old_sr, u8 *new_sr,\n+\t\t\t u8 pow, bool use_top)\n+{\n+\tu8 bp_mask = spi_nor_get_sr_bp_mask(nor);\n+\tu8 tb_mask = spi_nor_get_sr_tb_mask(nor);\n+\tint ret;\n+\n+\tnew_sr[0] = old_sr[0] & ~bp_mask & ~tb_mask;\n+\n+\t/* Build BP field */\n+\tret = spi_nor_sr_set_bp_mask(nor, &new_sr[0], pow);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Build TB field */\n+\tif (!use_top)\n+\t\tnew_sr[0] |= tb_mask;\n+\n+\treturn 0;\n+}\n+\n /*\n * Lock a region of the flash. Compatible with ST Micro and similar flash.\n * Supports the block protection bits BP{0,1,2}/BP{0,1,2,3} in the status\n@@ -162,11 +199,10 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, u64 len)\n \tint ret;\n \tu8 status_old[1] = {}, status_new[1] = {};\n \tu8 bp_mask = spi_nor_get_sr_bp_mask(nor);\n-\tu8 tb_mask = spi_nor_get_sr_tb_mask(nor);\n-\tu8 pow, val;\n \tloff_t lock_len;\n \tbool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;\n \tbool use_top;\n+\tu8 pow;\n \n \tret = spi_nor_read_sr(nor, nor->bouncebuf);\n \tif (ret)\n@@ -200,24 +236,19 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, u64 len)\n \t\tlock_len = ofs + len;\n \n \tif (lock_len == nor->params->size) {\n-\t\tval = bp_mask;\n+\t\tpow = (nor->flags & SNOR_F_HAS_4BIT_BP) ? GENMASK(3, 0) : GENMASK(2, 0);\n \t} else {\n \t\tmin_prot_len = spi_nor_get_min_prot_length_sr(nor);\n \t\tpow = ilog2(lock_len) - ilog2(min_prot_len) + 1;\n-\t\tval = pow << SR_BP_SHIFT;\n-\n-\t\tif (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3)\n-\t\t\tval = (val & ~SR_BP3) | SR_BP3_BIT6;\n-\n-\t\tif (val & ~bp_mask)\n-\t\t\treturn -EINVAL;\n-\n-\t\t/* Don't \"lock\" with no region! */\n-\t\tif (!(val & bp_mask))\n-\t\t\treturn -EINVAL;\n \t}\n \n-\tstatus_new[0] = (status_old[0] & ~bp_mask & ~tb_mask) | val;\n+\tret = spi_nor_build_sr(nor, status_old, status_new, pow, use_top);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Don't \"lock\" with no region! */\n+\tif (!(status_new[0] & bp_mask))\n+\t\treturn -EINVAL;\n \n \t/*\n \t * Disallow further writes if WP# pin is neither left floating nor\n@@ -227,9 +258,6 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, u64 len)\n \tif (!(nor->flags & SNOR_F_NO_WP))\n \t\tstatus_new[0] |= SR_SRWD;\n \n-\tif (!use_top)\n-\t\tstatus_new[0] |= tb_mask;\n-\n \t/* Don't bother if they're the same */\n \tif (status_new[0] == status_old[0])\n \t\treturn 0;\n@@ -252,11 +280,10 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, u64 len)\n \tint ret;\n \tu8 status_old[1], status_new[1];\n \tu8 bp_mask = spi_nor_get_sr_bp_mask(nor);\n-\tu8 tb_mask = spi_nor_get_sr_tb_mask(nor);\n-\tu8 pow, val;\n \tloff_t lock_len;\n \tbool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;\n \tbool use_top;\n+\tu8 pow;\n \n \tret = spi_nor_read_sr(nor, nor->bouncebuf);\n \tif (ret)\n@@ -297,29 +324,21 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, u64 len)\n \t\tlock_len = ofs;\n \n \tif (lock_len == 0) {\n-\t\tval = 0; /* fully unlocked */\n+\t\tpow = 0; /* fully unlocked */\n \t} else {\n \t\tmin_prot_len = spi_nor_get_min_prot_length_sr(nor);\n \t\tpow = ilog2(lock_len) - ilog2(min_prot_len) + 1;\n-\t\tval = pow << SR_BP_SHIFT;\n \n-\t\tif (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3)\n-\t\t\tval = (val & ~SR_BP3) | SR_BP3_BIT6;\n-\n-\t\t/* Some power-of-two sizes may not be supported */\n-\t\tif (val & ~bp_mask)\n-\t\t\treturn -EINVAL;\n \t}\n \n-\tstatus_new[0] = (status_old[0] & ~bp_mask & ~tb_mask) | val;\n+\tret = spi_nor_build_sr(nor, status_old, status_new, pow, use_top);\n+\tif (ret)\n+\t\treturn ret;\n \n \t/* Don't protect status register if we're fully unlocked */\n \tif (lock_len == 0)\n \t\tstatus_new[0] &= ~SR_SRWD;\n \n-\tif (!use_top)\n-\t\tstatus_new[0] |= tb_mask;\n-\n \t/* Don't bother if they're the same */\n \tif (status_new[0] == status_old[0])\n \t\treturn 0;\n","prefixes":["v4","13/27"]}