{"id":2219450,"url":"http://patchwork.ozlabs.org/api/patches/2219450/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260403022513.9446-4-alif.zakuan.yuslaimi@altera.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260403022513.9446-4-alif.zakuan.yuslaimi@altera.com>","list_archive_url":null,"date":"2026-04-03T02:25:07","name":"[v1,3/9] arm: socfpga: Move firmware register settings from source code to device tree","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"4a0b81ee7dfb0d356f2d63f85c5604cfb799661e","submitter":{"id":90458,"url":"http://patchwork.ozlabs.org/api/people/90458/?format=json","name":"Yuslaimi, Alif Zakuan","email":"alif.zakuan.yuslaimi@altera.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260403022513.9446-4-alif.zakuan.yuslaimi@altera.com/mbox/","series":[{"id":498580,"url":"http://patchwork.ozlabs.org/api/series/498580/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=498580","date":"2026-04-03T02:25:04","name":"SoCFPGA: Update Boot Support for Stratix10 in U-Boot","version":1,"mbox":"http://patchwork.ozlabs.org/series/498580/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2219450/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2219450/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=altera.com header.i=@altera.com header.a=rsa-sha256\n header.s=selector2 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phobos.denx.de","X-Virus-Status":"Clean"},"content":"From: Alif Zakuan Yuslaimi \n\nMigrate the CCU, firewall, and high privilege register configurations from\nhardcoded values in the source code to the device tree.\n\nThis helps to centralize hardware configuration, improves maintainability,\nand allows easier customization for different platforms.\n\nSigned-off-by: Alif Zakuan Yuslaimi \n---\n arch/arm/dts/socfpga_stratix10-u-boot.dtsi | 149 +++++++++++++++++++++\n arch/arm/mach-socfpga/spl_s10.c | 29 ++--\n drivers/ddr/altera/sdram_s10.c | 44 ------\n 3 files changed, 165 insertions(+), 57 deletions(-)","diff":"diff --git a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi\nindex a3b4c0564f9..ad4b383f704 100644\n--- a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi\n+++ b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi\n@@ -6,6 +6,7 @@\n * Copyright (C) 2026 Altera Corporation \n */\n \n+#include \"socfpga_soc64_u-boot.dtsi\"\n #include \"socfpga_soc64_fit-u-boot.dtsi\"\n \n /{\n@@ -134,6 +135,154 @@\n \tbootph-all;\n };\n \n+&socfpga_l3interconnect_firewall {\n+\ti_ccu_noc_registers@f7000000 {\n+\t\treg = <0xf7000000 0x00049e60>;\n+\t\tintel,offset-settings =\n+\t\t\t/* Enable access to DDR reg from CPU */\n+\t\t\t<0x0004400 0xF8000000 0xffffffff>,\n+\n+\t\t\t/* Enable access to DDR region from CPU */\n+\t\t\t<0x00045c0 0x00000000 0xffffffdf>,\n+\t\t\t<0x00045e0 0x00000000 0xffffffdf>,\n+\t\t\t<0x0004600 0x00000000 0xffffffdf>,\n+\t\t\t<0x0004620 0x00000000 0xffffffdf>,\n+\t\t\t<0x0004640 0x00000000 0xffffffdf>,\n+\t\t\t<0x0004660 0x00000000 0xffffffdf>,\n+\n+\t\t\t/* Disable ocram security at CCU for non secure access */\n+\t\t\t<0x0004688 0xfffc0000 0xffffffcf>,\n+\t\t\t<0x0018628 0xfffc0000 0xffffffcf>,\n+\n+\t\t\t/* Enable access to DDR region from IO master */\n+\t\t\t<0x00018560 0x00000000 0xffffffdf>,\n+\t\t\t<0x00018580 0x00000000 0xffffffdf>,\n+\t\t\t<0x000185a0 0x00000000 0xffffffdf>,\n+\t\t\t<0x000185c0 0x00000000 0xffffffdf>,\n+\t\t\t<0x000185e0 0x00000000 0xffffffdf>,\n+\t\t\t<0x00018600 0x00000000 0xffffffdf>,\n+\n+\t\t\t/* Enable access to DDR region from TCU */\n+\t\t\t<0x0002c520 0x00000000 0xffffffdf>,\n+\t\t\t<0x0002c540 0x00000000 0xffffffdf>,\n+\t\t\t<0x0002c560 0x00000000 0xffffffdf>,\n+\t\t\t<0x0002c580 0x00000000 0xffffffdf>,\n+\t\t\t<0x0002c5a0 0x00000000 0xffffffdf>,\n+\t\t\t<0x0002c5c0 0x00000000 0xffffffdf>,\n+\n+\t\t\t/* Enable access to DDR region from FPGA */\n+\t\t\t<0x000105a0 0x00000000 0xffffffdf>,\n+\t\t\t<0x000105c0 0x00000000 0xffffffdf>,\n+\t\t\t<0x000105e0 0x00000000 0xffffffdf>,\n+\t\t\t<0x00010600 0x00000000 0xffffffdf>,\n+\t\t\t<0x00010620 0x00000000 0xffffffdf>,\n+\t\t\t<0x00010640 0x00000000 0xffffffdf>;\n+\t\tbootph-all;\n+\t};\n+\n+\t/*\n+\t * Both firewall and QOS regs accessed by CPU in MPFE has\n+\t * dependency on CCU configuration above.\n+\t *\n+\t * Below are all fpga2sdram firewall settings with default\n+\t * reset value for the sake of easy reference by users.\n+\t * Users may choose to remove any of these register configurations\n+\t * that they do not require in their specific implementation.\n+\t */\n+\tsoc_noc_fw_ddr_fpga2sdram_inst_0_ddr_scr@f8020200 {\n+\t\treg = <0xf8020200 0x00000050>;\n+\t\tintel,offset-settings =\n+\t\t\t<0x0000000 0x00000000 0x0000000f>,\n+\t\t\t<0x0000004 0x00000000 0x0000000f>,\n+\t\t\t<0x0000008 0x00000000 0x0000000f>,\n+\t\t\t<0x0000010 0x00000000 0xffff0000>,\n+\t\t\t<0x0000014 0x00000000 0x0000001f>,\n+\t\t\t<0x0000018 0x00000000 0xffff0000>,\n+\t\t\t<0x000001c 0x00000000 0x0000001f>,\n+\t\t\t<0x0000020 0x00000000 0xffff0000>,\n+\t\t\t<0x0000024 0x00000000 0x0000001f>,\n+\t\t\t<0x0000028 0x00000000 0xffff0000>,\n+\t\t\t<0x000002c 0x00000000 0x0000001f>,\n+\t\t\t<0x0000030 0x00000000 0xffff0000>,\n+\t\t\t<0x0000034 0x00000000 0x0000001f>,\n+\t\t\t<0x0000038 0x00000000 0xffff0000>,\n+\t\t\t<0x000003c 0x00000000 0x0000001f>,\n+\t\t\t<0x0000040 0x00000000 0xffff0000>,\n+\t\t\t<0x0000044 0x00000000 0x0000001f>,\n+\t\t\t<0x0000048 0x00000000 0xffff0000>,\n+\t\t\t<0x000004c 0x00000000 0x0000001f>;\n+\t\tbootph-all;\n+\t};\n+\n+\tsoc_noc_fw_ddr_fpga2sdram_inst_1_ddr_scr@f8020300 {\n+\t\treg = <0xf8020300 0x00000050>;\n+\t\tintel,offset-settings =\n+\t\t\t<0x0000000 0x00000000 0x0000000f>,\n+\t\t\t<0x0000004 0x00000000 0x0000000f>,\n+\t\t\t<0x0000008 0x00000000 0x0000000f>,\n+\t\t\t<0x0000010 0x00000000 0xffff0000>,\n+\t\t\t<0x0000014 0x00000000 0x0000001f>,\n+\t\t\t<0x0000018 0x00000000 0xffff0000>,\n+\t\t\t<0x000001c 0x00000000 0x0000001f>,\n+\t\t\t<0x0000020 0x00000000 0xffff0000>,\n+\t\t\t<0x0000024 0x00000000 0x0000001f>,\n+\t\t\t<0x0000028 0x00000000 0xffff0000>,\n+\t\t\t<0x000002c 0x00000000 0x0000001f>,\n+\t\t\t<0x0000030 0x00000000 0xffff0000>,\n+\t\t\t<0x0000034 0x00000000 0x0000001f>,\n+\t\t\t<0x0000038 0x00000000 0xffff0000>,\n+\t\t\t<0x000003c 0x00000000 0x0000001f>,\n+\t\t\t<0x0000040 0x00000000 0xffff0000>,\n+\t\t\t<0x0000044 0x00000000 0x0000001f>,\n+\t\t\t<0x0000048 0x00000000 0xffff0000>,\n+\t\t\t<0x000004c 0x00000000 0x0000001f>;\n+\t\tbootph-all;\n+\t};\n+\n+\tsoc_noc_fw_ddr_fpga2sdram_inst_2_ddr_scr@f8020400 {\n+\t\treg = <0xf8020400 0x00000050>;\n+\t\tintel,offset-settings =\n+\t\t\t<0x0000000 0x00000000 0x0000000f>,\n+\t\t\t<0x0000004 0x00000000 0x0000000f>,\n+\t\t\t<0x0000008 0x00000000 0x0000000f>,\n+\t\t\t<0x0000010 0x00000000 0xffff0000>,\n+\t\t\t<0x0000014 0x00000000 0x0000001f>,\n+\t\t\t<0x0000018 0x00000000 0xffff0000>,\n+\t\t\t<0x000001c 0x00000000 0x0000001f>,\n+\t\t\t<0x0000020 0x00000000 0xffff0000>,\n+\t\t\t<0x0000024 0x00000000 0x0000001f>,\n+\t\t\t<0x0000028 0x00000000 0xffff0000>,\n+\t\t\t<0x000002c 0x00000000 0x0000001f>,\n+\t\t\t<0x0000030 0x00000000 0xffff0000>,\n+\t\t\t<0x0000034 0x00000000 0x0000001f>,\n+\t\t\t<0x0000038 0x00000000 0xffff0000>,\n+\t\t\t<0x000003c 0x00000000 0x0000001f>,\n+\t\t\t<0x0000040 0x00000000 0xffff0000>,\n+\t\t\t<0x0000044 0x00000000 0x0000001f>,\n+\t\t\t<0x0000048 0x00000000 0xffff0000>,\n+\t\t\t<0x000004c 0x00000000 0x0000001f>;\n+\t\tbootph-all;\n+\t};\n+\n+\t/*\n+\t * Example of ccu_mem0_I_main QOS settings with\n+\t * default reset value for the sake of easy reference\n+\t * by users. Users may choose to remove any of these register\n+\t * configurations that they do not require in their specific\n+\t * implementation.\n+\t */\n+\tsoc_ddr_scheduler_inst_0_ccu_mem0_I_main_QosGenerator@f8022080 {\n+\t\treg = <0xf8022080 0x0000001c>;\n+\t\tintel,offset-settings =\n+\t\t\t<0x0000008 0x00000000 0x00000303>,\n+\t\t\t<0x000000c 0x00000001 0x00000003>,\n+\t\t\t<0x0000010 0x00000BFE 0x00001fff>,\n+\t\t\t<0x0000014 0x00000008 0x000003ff>,\n+\t\t\t<0x0000018 0x00000000 0x00000007>;\n+\t\tbootph-all;\n+\t};\n+};\n+\n &uart0 {\n \tbootph-all;\n \tclock-frequency = <100000000>;\ndiff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c\nindex a0d3c96d456..8ab80740c6e 100644\n--- a/arch/arm/mach-socfpga/spl_s10.c\n+++ b/arch/arm/mach-socfpga/spl_s10.c\n@@ -25,6 +25,7 @@ void board_init_f(ulong dummy)\n {\n \tconst struct cm_config *cm_default_cfg = cm_get_default_config();\n \tint ret;\n+\tstruct udevice *dev;\n \n \tret = spl_early_init();\n \tif (ret)\n@@ -67,22 +68,24 @@ void board_init_f(ulong dummy)\n \tprint_reset_info();\n \tcm_print_clock_quick_summary();\n \n-\tfirewall_setup();\n+\tret = uclass_get_device_by_name(UCLASS_NOP, \"socfpga-system-mgr-firewall\", &dev);\n+\tif (ret) {\n+\t\tprintf(\"System manager firewall configuration failed: %d\\n\", ret);\n+\t\thang();\n+\t}\n \n-\t/* disable ocram security at CCU for non secure access */\n-\tclrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0),\n-\t\t CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);\n-\tclrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0),\n-\t\t CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);\n+\tret = uclass_get_device_by_name(UCLASS_NOP, \"socfpga-l3interconnect-firewall\", &dev);\n+\tif (ret) {\n+\t\tprintf(\"L3 interconnect firewall configuration failed: %d\\n\", ret);\n+\t\thang();\n+\t}\n \n #if CONFIG_IS_ENABLED(ALTERA_SDRAM)\n-\t\tstruct udevice *dev;\n-\n-\t\tret = uclass_get_device(UCLASS_RAM, 0, &dev);\n-\t\tif (ret) {\n-\t\t\tdebug(\"DRAM init failed: %d\\n\", ret);\n-\t\t\thang();\n-\t\t}\n+\tret = uclass_get_device(UCLASS_RAM, 0, &dev);\n+\tif (ret) {\n+\t\tdebug(\"DRAM init failed: %d\\n\", ret);\n+\t\thang();\n+\t}\n #endif\n \n #ifdef CONFIG_CADENCE_QSPI\ndiff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c\nindex 4ac4c79e0ac..1497a8e4aab 100644\n--- a/drivers/ddr/altera/sdram_s10.c\n+++ b/drivers/ddr/altera/sdram_s10.c\n@@ -78,50 +78,6 @@ int sdram_mmr_init_full(struct udevice *dev)\n \tphys_size_t hw_size;\n \tstruct bd_info bd = {0};\n \n-\t/* Enable access to DDR from CPU master */\n-\tclrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_DDRREG),\n-\t\t CCU_ADBASE_DI_MASK);\n-\tclrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE0),\n-\t\t CCU_ADBASE_DI_MASK);\n-\tclrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1A),\n-\t\t CCU_ADBASE_DI_MASK);\n-\tclrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1B),\n-\t\t CCU_ADBASE_DI_MASK);\n-\tclrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1C),\n-\t\t CCU_ADBASE_DI_MASK);\n-\tclrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1D),\n-\t\t CCU_ADBASE_DI_MASK);\n-\tclrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1E),\n-\t\t CCU_ADBASE_DI_MASK);\n-\n-\t/* Enable access to DDR from IO master */\n-\tclrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE0),\n-\t\t CCU_ADBASE_DI_MASK);\n-\tclrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1A),\n-\t\t CCU_ADBASE_DI_MASK);\n-\tclrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1B),\n-\t\t CCU_ADBASE_DI_MASK);\n-\tclrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1C),\n-\t\t CCU_ADBASE_DI_MASK);\n-\tclrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1D),\n-\t\t CCU_ADBASE_DI_MASK);\n-\tclrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1E),\n-\t\t CCU_ADBASE_DI_MASK);\n-\n-\t/* Enable access to DDR from TCU */\n-\tclrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE0),\n-\t\t CCU_ADBASE_DI_MASK);\n-\tclrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1A),\n-\t\t CCU_ADBASE_DI_MASK);\n-\tclrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1B),\n-\t\t CCU_ADBASE_DI_MASK);\n-\tclrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1C),\n-\t\t CCU_ADBASE_DI_MASK);\n-\tclrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1D),\n-\t\t CCU_ADBASE_DI_MASK);\n-\tclrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1E),\n-\t\t CCU_ADBASE_DI_MASK);\n-\n \t/* this enables nonsecure access to DDR */\n \t/* mpuregion0addr_limit */\n \tFW_MPU_DDR_SCR_WRITEL(0xFFFF0000, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);\n","prefixes":["v1","3/9"]}