{"id":2219053,"url":"http://patchwork.ozlabs.org/api/patches/2219053/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/4bbaed1625dba497aa7838d5417dd0cad4c10e22.1775122853.git.matheus.bernardino@oss.qualcomm.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<4bbaed1625dba497aa7838d5417dd0cad4c10e22.1775122853.git.matheus.bernardino@oss.qualcomm.com>","list_archive_url":null,"date":"2026-04-02T10:47:31","name":"[v2,14/16] tests/hexagon: add tests for v68 HVX IEEE float conversions","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"16144fa2faf5db900280bf86a331d88489e5abc9","submitter":{"id":90606,"url":"http://patchwork.ozlabs.org/api/people/90606/?format=json","name":"Matheus Tavares Bernardino","email":"matheus.bernardino@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/4bbaed1625dba497aa7838d5417dd0cad4c10e22.1775122853.git.matheus.bernardino@oss.qualcomm.com/mbox/","series":[{"id":498468,"url":"http://patchwork.ozlabs.org/api/series/498468/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498468","date":"2026-04-02T10:47:20","name":"hexagon: add missing HVX float instructions","version":2,"mbox":"http://patchwork.ozlabs.org/series/498468/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2219053/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2219053/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=aBpt8IhU;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=OfsbNJco;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n 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","To":"qemu-devel@nongnu.org","Cc":"richard.henderson@linaro.org, ale@rev.ng, anjo@rev.ng,\n brian.cain@oss.qualcomm.com, ltaylorsimpson@gmail.com,\n marco.liebel@oss.qualcomm.com, philmd@linaro.org,\n quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com","Subject":"[PATCH v2 14/16] tests/hexagon: add tests for v68 HVX IEEE float\n conversions","Date":"Thu, 2 Apr 2026 03:47:31 -0700","Message-Id":"\n <4bbaed1625dba497aa7838d5417dd0cad4c10e22.1775122853.git.matheus.bernardino@oss.qualcomm.com>","X-Mailer":"git-send-email 2.37.2","In-Reply-To":"","References":"","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Authority-Analysis":"v=2.4 cv=TqLrRTXh c=1 sm=1 tr=0 ts=69ce4956 cx=c_pps\n a=Uww141gWH0fZj/3QKPojxA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8\n a=tBVvuLY118niWomA0oIA:9 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","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Signed-off-by: Matheus Tavares Bernardino \n---\n tests/tcg/hexagon/hex_test.h | 14 +++\n tests/tcg/hexagon/hvx_misc.h | 2 +\n tests/tcg/hexagon/fp_hvx_cvt.c | 188 ++++++++++++++++++++++++++++++\n tests/tcg/hexagon/Makefile.target | 3 +\n 4 files changed, 207 insertions(+)\n create mode 100644 tests/tcg/hexagon/fp_hvx_cvt.c","diff":"diff --git a/tests/tcg/hexagon/hex_test.h b/tests/tcg/hexagon/hex_test.h\nindex e7a6644d41..d5da8ad240 100644\n--- a/tests/tcg/hexagon/hex_test.h\n+++ b/tests/tcg/hexagon/hex_test.h\n@@ -111,6 +111,20 @@ static inline void __check64_ne(int line, uint64_t val, uint64_t expect)\n \"usr = r2\\n\\t\"\n \n /* Some useful floating point values */\n+const uint16_t HF_INF = 0x7c00;\n+const uint16_t HF_INF_neg = 0xfc00;\n+const uint16_t HF_QNaN = 0x7e00;\n+const uint16_t HF_SNaN = 0x7d00;\n+const uint16_t HF_QNaN_neg = 0xfe00;\n+const uint16_t HF_zero = 0x0000;\n+const uint16_t HF_zero_neg = 0x8000;\n+const uint16_t HF_one = 0x3c00;\n+const uint16_t HF_one_recip = 0x3bf9;\n+const uint16_t HF_two = 0x4000;\n+const uint16_t HF_small_neg = 0x8010;\n+const uint16_t HF_any = 0x3c00;\n+const uint16_t HF_neg_two = 0xc000;\n+\n const uint32_t SF_INF = 0x7f800000;\n const uint32_t SF_INF_neg = 0xff800000;\n const uint32_t SF_QNaN = 0x7fc00000;\ndiff --git a/tests/tcg/hexagon/hvx_misc.h b/tests/tcg/hexagon/hvx_misc.h\nindex 0330cb289d..43de20da6a 100644\n--- a/tests/tcg/hexagon/hvx_misc.h\n+++ b/tests/tcg/hexagon/hvx_misc.h\n@@ -69,7 +69,9 @@ CHECK_OUTPUT_FUNC(d, 8)\n CHECK_OUTPUT_FUNC(w, 4)\n CHECK_OUTPUT_FUNC(sf, 4)\n CHECK_OUTPUT_FUNC(h, 2)\n+CHECK_OUTPUT_FUNC(uh, 2)\n CHECK_OUTPUT_FUNC(hf, 2)\n+CHECK_OUTPUT_FUNC(ub, 1)\n CHECK_OUTPUT_FUNC(b, 1)\n \n static inline void init_buffers(void)\ndiff --git a/tests/tcg/hexagon/fp_hvx_cvt.c b/tests/tcg/hexagon/fp_hvx_cvt.c\nnew file mode 100644\nindex 0000000000..71c3f0fd4f\n--- /dev/null\n+++ b/tests/tcg/hexagon/fp_hvx_cvt.c\n@@ -0,0 +1,188 @@\n+/*\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+\n+#if __HEXAGON_ARCH__ > 75\n+#error \"After v75, compiler will replace some FP HVX instructions.\"\n+#endif\n+\n+int err;\n+#include \"hvx_misc.h\"\n+#include \"hex_test.h\"\n+\n+#define TEST_EXP(TO, FROM, VAL, EXP) do { \\\n+ ((MMVector *)&buffer)->FROM[index] = VAL; \\\n+ expect[0].TO[index] = EXP; \\\n+ index++; \\\n+} while (0)\n+\n+#define DEF_TEST_CVT(TO, FROM, TESTS) \\\n+ static void test_vcvt_##TO##_##FROM(void) \\\n+ { \\\n+ HVX_Vector *hvx_output = (HVX_Vector *)&output[0]; \\\n+ HVX_Vector buffer; \\\n+ int index = 0; \\\n+ memset(&buffer, 0, sizeof(buffer)); \\\n+ memset(expect, 0, sizeof(expect)); \\\n+ TESTS \\\n+ *hvx_output = Q6_V##TO##_vcvt_V##FROM(buffer); \\\n+ check_output_##TO(__LINE__, 1); \\\n+ }\n+\n+DEF_TEST_CVT(uh, hf, { \\\n+ TEST_EXP(uh, hf, HF_QNaN, UINT16_MAX); \\\n+ TEST_EXP(uh, hf, HF_SNaN, UINT16_MAX); \\\n+ TEST_EXP(uh, hf, HF_QNaN_neg, UINT16_MAX); \\\n+ TEST_EXP(uh, hf, HF_INF, UINT16_MAX); \\\n+ TEST_EXP(uh, hf, HF_INF_neg, 0); \\\n+ TEST_EXP(uh, hf, HF_neg_two, 0); \\\n+ TEST_EXP(uh, hf, HF_zero_neg, 0); \\\n+ TEST_EXP(uh, hf, raw_hf((_Float16)2.1), 2); \\\n+ TEST_EXP(uh, hf, HF_one_recip, 1); \\\n+})\n+\n+DEF_TEST_CVT(h, hf, { \\\n+ TEST_EXP(h, hf, HF_QNaN, INT16_MAX); \\\n+ TEST_EXP(h, hf, HF_SNaN, INT16_MAX); \\\n+ TEST_EXP(h, hf, HF_QNaN_neg, INT16_MAX); \\\n+ TEST_EXP(h, hf, HF_INF, INT16_MAX); \\\n+ TEST_EXP(h, hf, HF_INF_neg, INT16_MIN); \\\n+ TEST_EXP(h, hf, HF_neg_two, -2); \\\n+ TEST_EXP(h, hf, HF_zero_neg, 0); \\\n+ TEST_EXP(h, hf, raw_hf((_Float16)2.1), 2); \\\n+ TEST_EXP(h, hf, HF_one_recip, 1); \\\n+})\n+\n+/*\n+ * Some cvt operations take two vectors as input and perform the following:\n+ * VdV.TO[4*i] = OP(VuV.FROM[2*i]);\n+ * VdV.TO[4*i+1] = OP(VuV.FROM[2*i+1]);\n+ * VdV.TO[4*i+2] = OP(VvV.FROM[2*i]);\n+ * VdV.TO[4*i+3] = OP(VvV.FROM[2*i+1]))\n+ * We use bf_index and index in a way that the tests are always done either\n+ * using the first or third line of the above snippet.\n+ */\n+#define TEST_EXP_2(TO, FROM, VAL, EXP) do { \\\n+ ((MMVector *)&buffers[bf_index])->FROM[2 * index] = VAL; \\\n+ expect[0].TO[(4 * index) + (2 * bf_index)] = EXP; \\\n+ index++; \\\n+ bf_index = (bf_index + 1) % 2; \\\n+} while (0)\n+\n+#define DEF_TEST_CVT_2(TO, FROM, TESTS) \\\n+ static void test_vcvt_##TO##_##FROM(void) \\\n+ { \\\n+ HVX_Vector *hvx_output = (HVX_Vector *)&output[0]; \\\n+ HVX_Vector buffers[2]; \\\n+ int index = 0, bf_index = 0; \\\n+ memset(&buffers, 0, sizeof(buffers)); \\\n+ memset(expect, 0, sizeof(expect)); \\\n+ TESTS \\\n+ *hvx_output = Q6_V##TO##_vcvt_V##FROM##V##FROM(buffers[0], buffers[1]); \\\n+ check_output_##TO(__LINE__, 1); \\\n+ }\n+\n+DEF_TEST_CVT_2(ub, hf, { \\\n+ TEST_EXP_2(ub, hf, HF_QNaN, UINT8_MAX); \\\n+ TEST_EXP_2(ub, hf, HF_SNaN, UINT8_MAX); \\\n+ TEST_EXP_2(ub, hf, HF_QNaN_neg, UINT8_MAX); \\\n+ TEST_EXP_2(ub, hf, HF_INF, UINT8_MAX); \\\n+ TEST_EXP_2(ub, hf, HF_INF_neg, 0); \\\n+ TEST_EXP_2(ub, hf, HF_small_neg, 0); \\\n+ TEST_EXP_2(ub, hf, HF_neg_two, 0); \\\n+ TEST_EXP_2(ub, hf, HF_zero_neg, 0); \\\n+ TEST_EXP_2(ub, hf, raw_hf((_Float16)2.1), 2); \\\n+ TEST_EXP_2(ub, hf, HF_one_recip, 1); \\\n+})\n+\n+DEF_TEST_CVT_2(b, hf, { \\\n+ TEST_EXP_2(b, hf, HF_QNaN, INT8_MAX); \\\n+ TEST_EXP_2(b, hf, HF_SNaN, INT8_MAX); \\\n+ TEST_EXP_2(b, hf, HF_QNaN_neg, INT8_MAX); \\\n+ TEST_EXP_2(b, hf, HF_INF, INT8_MAX); \\\n+ TEST_EXP_2(b, hf, HF_INF_neg, INT8_MIN); \\\n+ TEST_EXP_2(b, hf, HF_small_neg, 0); \\\n+ TEST_EXP_2(b, hf, HF_neg_two, -2); \\\n+ TEST_EXP_2(b, hf, HF_zero_neg, 0); \\\n+ TEST_EXP_2(b, hf, raw_hf((_Float16)2.1), 2); \\\n+ TEST_EXP_2(b, hf, HF_one_recip, 1); \\\n+})\n+\n+#define DEF_TEST_VCONV(TO, FROM, TESTS) \\\n+ static void test_vconv_##TO##_##FROM(void) \\\n+ { \\\n+ HVX_Vector *hvx_output = (HVX_Vector *)&output[0]; \\\n+ HVX_Vector buffer; \\\n+ int index = 0; \\\n+ memset(&buffer, 0, sizeof(buffer)); \\\n+ memset(expect, 0, sizeof(expect)); \\\n+ TESTS \\\n+ *hvx_output = Q6_V##TO##_equals_V##FROM(buffer); \\\n+ check_output_##TO(__LINE__, 1); \\\n+ }\n+\n+DEF_TEST_VCONV(w, sf, { \\\n+ TEST_EXP(w, sf, SF_QNaN, INT32_MAX); \\\n+ TEST_EXP(w, sf, SF_SNaN, INT32_MAX); \\\n+ TEST_EXP(w, sf, SF_QNaN_neg, INT32_MIN); \\\n+ TEST_EXP(w, sf, SF_INF, INT32_MAX); \\\n+ TEST_EXP(w, sf, SF_INF_neg, INT32_MIN); \\\n+ TEST_EXP(w, sf, SF_small_neg, 0); \\\n+ TEST_EXP(w, sf, SF_neg_two, -2); \\\n+ TEST_EXP(w, sf, SF_zero_neg, 0); \\\n+ TEST_EXP(w, sf, raw_sf(2.1f), 2); \\\n+ TEST_EXP(w, sf, raw_sf(2.8f), 2); \\\n+})\n+\n+DEF_TEST_VCONV(h, hf, { \\\n+ TEST_EXP(h, hf, HF_QNaN, INT16_MAX); \\\n+ TEST_EXP(h, hf, HF_SNaN, INT16_MAX); \\\n+ TEST_EXP(h, hf, HF_QNaN_neg, INT16_MIN); \\\n+ TEST_EXP(h, hf, HF_INF, INT16_MAX); \\\n+ TEST_EXP(h, hf, HF_INF_neg, INT16_MIN); \\\n+ TEST_EXP(h, hf, HF_small_neg, 0); \\\n+ TEST_EXP(h, hf, HF_neg_two, -2); \\\n+ TEST_EXP(h, hf, HF_zero_neg, 0); \\\n+ TEST_EXP(h, hf, raw_hf((_Float16)2.1), 2); \\\n+ TEST_EXP(h, hf, raw_hf((_Float16)2.8), 2); \\\n+})\n+\n+DEF_TEST_VCONV(hf, h, { \\\n+ TEST_EXP(hf, h, 0, HF_zero); \\\n+ TEST_EXP(hf, h, 2, HF_two); \\\n+ TEST_EXP(hf, h, -2, HF_neg_two); \\\n+ TEST_EXP(hf, h, 2049, raw_hf((_Float16)2048)); /* rounds DOWN */ \\\n+ TEST_EXP(hf, h, 2051, raw_hf((_Float16)2052)); /* rounds UP */ \\\n+})\n+\n+DEF_TEST_VCONV(sf, w, { \\\n+ TEST_EXP(sf, w, 0, SF_zero); \\\n+ TEST_EXP(sf, w, 2, SF_two); \\\n+ TEST_EXP(sf, w, -2, SF_neg_two); \\\n+ TEST_EXP(sf, w, 16777217, raw_sf((float)16777216)); /* rounds DOWN */ \\\n+ TEST_EXP(sf, w, 16777219, raw_sf((float)16777220)); /* rounds UP */ \\\n+})\n+\n+int main(void)\n+{\n+ test_vcvt_uh_hf();\n+ test_vcvt_h_hf();\n+ test_vcvt_ub_hf();\n+ test_vcvt_b_hf();\n+ test_vconv_w_sf();\n+ test_vconv_sf_w();\n+ test_vconv_h_hf();\n+ test_vconv_hf_h();\n+\n+ puts(err ? \"FAIL\" : \"PASS\");\n+ return err ? 1 : 0;\n+}\ndiff --git a/tests/tcg/hexagon/Makefile.target b/tests/tcg/hexagon/Makefile.target\nindex 789721bdac..83969e0e73 100644\n--- a/tests/tcg/hexagon/Makefile.target\n+++ b/tests/tcg/hexagon/Makefile.target\n@@ -51,6 +51,7 @@ HEX_TESTS += scatter_gather\n HEX_TESTS += hvx_misc\n HEX_TESTS += hvx_histogram\n HEX_TESTS += fp_hvx\n+HEX_TESTS += fp_hvx_cvt\n HEX_TESTS += fp_hvx_disabled\n HEX_TESTS += invalid-slots\n HEX_TESTS += invalid-encoding\n@@ -132,6 +133,8 @@ fp_hvx: fp_hvx.c hvx_misc.h\n fp_hvx: CFLAGS += -mhvx -mhvx-ieee-fp\n fp_hvx_disabled: fp_hvx_disabled.c hvx_misc.h\n fp_hvx_disabled: CFLAGS += -mhvx -mhvx-ieee-fp\n+fp_hvx_cvt: fp_hvx_cvt.c hvx_misc.h\n+fp_hvx_cvt: CFLAGS += -mhvx -mhvx-ieee-fp\n \n run-fp_hvx_disabled: QEMU_OPTS += -cpu v73,ieee-fp=false\n \n","prefixes":["v2","14/16"]}