{"id":2219044,"url":"http://patchwork.ozlabs.org/api/patches/2219044/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/cbb8794e47694bbb0576313b882dd0ecc525cef1.1775122853.git.matheus.bernardino@oss.qualcomm.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2026-04-02T10:47:20","name":"[v2,03/16] target/hexagon/cpu: add HVX IEEE FP extension","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"325d3c522c28fca6331f8a99ec517b8a8e8afb5b","submitter":{"id":90606,"url":"http://patchwork.ozlabs.org/api/people/90606/?format=json","name":"Matheus Tavares Bernardino","email":"matheus.bernardino@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/cbb8794e47694bbb0576313b882dd0ecc525cef1.1775122853.git.matheus.bernardino@oss.qualcomm.com/mbox/","series":[{"id":498468,"url":"http://patchwork.ozlabs.org/api/series/498468/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498468","date":"2026-04-02T10:47:20","name":"hexagon: add missing HVX float instructions","version":2,"mbox":"http://patchwork.ozlabs.org/series/498468/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2219044/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2219044/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=a5c0nS5C;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=MriGsqBr;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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When unavailable, the\ninstruction effectively only set the destination registers to 0.\n\nSigned-off-by: Matheus Tavares Bernardino \n---\n target/hexagon/cpu.h | 1 +\n target/hexagon/translate.h | 1 +\n target/hexagon/attribs_def.h.inc | 3 +++\n target/hexagon/cpu.c | 1 +\n target/hexagon/translate.c | 1 +\n target/hexagon/gen_tcg_funcs.py | 11 ++++++++++\n target/hexagon/hex_common.py | 35 ++++++++++++++++++++++++++++++++\n 7 files changed, 53 insertions(+)","diff":"diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h\nindex 85afd59277..77822a48b6 100644\n--- a/target/hexagon/cpu.h\n+++ b/target/hexagon/cpu.h\n@@ -127,6 +127,7 @@ struct ArchCPU {\n bool lldb_compat;\n target_ulong lldb_stack_adjust;\n bool short_circuit;\n+ bool ieee_fp_extension;\n };\n \n #include \"cpu_bits.h\"\ndiff --git a/target/hexagon/translate.h b/target/hexagon/translate.h\nindex b37cb49238..516aab7038 100644\n--- a/target/hexagon/translate.h\n+++ b/target/hexagon/translate.h\n@@ -70,6 +70,7 @@ typedef struct DisasContext {\n target_ulong branch_dest;\n bool is_tight_loop;\n bool short_circuit;\n+ bool ieee_fp_extension;\n bool read_after_write;\n bool has_hvx_overlap;\n TCGv new_value[TOTAL_PER_THREAD_REGS];\ndiff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.h.inc\nindex 9e3a05f882..c85cd5d17c 100644\n--- a/target/hexagon/attribs_def.h.inc\n+++ b/target/hexagon/attribs_def.h.inc\n@@ -173,5 +173,8 @@ DEF_ATTRIB(NOTE_SHIFT_RESOURCE, \"Uses the HVX shift resource.\", \"\", \"\")\n DEF_ATTRIB(RESTRICT_NOSLOT1_STORE, \"Packet must not have slot 1 store\", \"\", \"\")\n DEF_ATTRIB(RESTRICT_LATEPRED, \"Predicate can not be used as a .new.\", \"\", \"\")\n \n+/* HVX IEEE FP extension attributes */\n+DEF_ATTRIB(HVX_IEEE_FP, \"HVX IEEE FP extension instruction\", \"\", \"\")\n+\n /* Keep this as the last attribute: */\n DEF_ATTRIB(ZZ_LASTATTRIB, \"Last attribute in the file\", \"\", \"\")\ndiff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c\nindex ffd14bb467..8b72a5d3c8 100644\n--- a/target/hexagon/cpu.c\n+++ b/target/hexagon/cpu.c\n@@ -54,6 +54,7 @@ static const Property hexagon_cpu_properties[] = {\n DEFINE_PROP_UNSIGNED(\"lldb-stack-adjust\", HexagonCPU, lldb_stack_adjust, 0,\n qdev_prop_uint32, target_ulong),\n DEFINE_PROP_BOOL(\"short-circuit\", HexagonCPU, short_circuit, true),\n+ DEFINE_PROP_BOOL(\"ieee-fp\", HexagonCPU, ieee_fp_extension, true),\n };\n \n const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = {\ndiff --git a/target/hexagon/translate.c b/target/hexagon/translate.c\nindex 633401451d..fa8f615a9e 100644\n--- a/target/hexagon/translate.c\n+++ b/target/hexagon/translate.c\n@@ -988,6 +988,7 @@ static void hexagon_tr_init_disas_context(DisasContextBase *dcbase,\n ctx->branch_cond = TCG_COND_NEVER;\n ctx->is_tight_loop = FIELD_EX32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP);\n ctx->short_circuit = hex_cpu->short_circuit;\n+ ctx->ieee_fp_extension = hex_cpu->ieee_fp_extension;\n }\n \n static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu)\ndiff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs.py\nindex 87b7f10d7f..b752ec883c 100755\n--- a/target/hexagon/gen_tcg_funcs.py\n+++ b/target/hexagon/gen_tcg_funcs.py\n@@ -22,6 +22,14 @@\n import string\n import hex_common\n \n+def gen_disabled_ieee_insn(f, tag, regs):\n+ f.write(\" if (!ctx->ieee_fp_extension) {\\n\")\n+ for regtype, regid in regs:\n+ reg = hex_common.get_register(tag, regtype, regid)\n+ if reg.is_hvx_reg() and reg.is_written():\n+ reg.gen_zero(f)\n+ f.write(\" return;\\n\")\n+ f.write(\" }\\n\")\n \n ##\n ## Generate the TCG code to call the helper\n@@ -62,6 +70,9 @@ def gen_tcg_func(f, tag, regs, imms):\n i = 1 if immlett.isupper() else 0\n f.write(f\" int {hex_common.imm_name(immlett)} = insn->immed[{i}];\\n\")\n \n+ if \"A_HVX_IEEE_FP\" in hex_common.attribdict[tag]:\n+ gen_disabled_ieee_insn(f, tag, regs)\n+\n if hex_common.is_idef_parser_enabled(tag):\n declared = []\n ## Handle registers\ndiff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py\nindex c0e9f26aeb..32a61505ce 100755\n--- a/target/hexagon/hex_common.py\n+++ b/target/hexagon/hex_common.py\n@@ -723,6 +723,11 @@ def decl_tcg(self, f, tag, regno):\n TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();\n tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});\n \"\"\"))\n+ def gen_zero(self, f):\n+ f.write(code_fmt(f\"\"\"\\\n+ tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()},\n+ sizeof(MMVector), sizeof(MMVector), 0);\n+ \"\"\"))\n def gen_write(self, f, tag):\n pass\n def helper_hvx_desc(self, f):\n@@ -789,6 +794,11 @@ def decl_tcg(self, f, tag, regno):\n TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();\n tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});\n \"\"\"))\n+ def gen_zero(self, f):\n+ f.write(code_fmt(f\"\"\"\\\n+ tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()},\n+ sizeof(MMVector), sizeof(MMVector), 0);\n+ \"\"\"))\n def gen_write(self, f, tag):\n pass\n def helper_hvx_desc(self, f):\n@@ -821,6 +831,11 @@ def decl_tcg(self, f, tag, regno):\n vreg_src_off(ctx, {self.reg_num}),\n sizeof(MMVector), sizeof(MMVector));\n \"\"\"))\n+ def gen_zero(self, f):\n+ f.write(code_fmt(f\"\"\"\\\n+ tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()},\n+ sizeof(MMVector), sizeof(MMVector), 0);\n+ \"\"\"))\n def gen_write(self, f, tag):\n f.write(code_fmt(f\"\"\"\\\n gen_vreg_write(ctx, {self.hvx_off()}, {self.reg_num},\n@@ -854,6 +869,11 @@ def decl_tcg(self, f, tag, regno):\n TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();\n tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});\n \"\"\"))\n+ def gen_zero(self, f):\n+ f.write(code_fmt(f\"\"\"\\\n+ tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()},\n+ sizeof(MMVectorPair), sizeof(MMVectorPair), 0);\n+ \"\"\"))\n def gen_write(self, f, tag):\n pass\n def helper_hvx_desc(self, f):\n@@ -913,6 +933,11 @@ def decl_tcg(self, f, tag, regno):\n TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();\n tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});\n \"\"\"))\n+ def gen_zero(self, f):\n+ f.write(code_fmt(f\"\"\"\\\n+ tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()},\n+ sizeof(MMVectorPair), sizeof(MMVectorPair), 0);\n+ \"\"\"))\n def gen_write(self, f, tag):\n f.write(code_fmt(f\"\"\"\\\n gen_vreg_write_pair(ctx, {self.hvx_off()}, {self.reg_num},\n@@ -946,6 +971,11 @@ def decl_tcg(self, f, tag, regno):\n TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();\n tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});\n \"\"\"))\n+ def gen_zero(self, f):\n+ f.write(code_fmt(f\"\"\"\\\n+ tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()},\n+ sizeof(MMQReg), sizeof(MMQReg), 0);\n+ \"\"\"))\n def gen_write(self, f, tag):\n pass\n def helper_hvx_desc(self, f):\n@@ -993,6 +1023,11 @@ def decl_tcg(self, f, tag, regno):\n TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();\n tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});\n \"\"\"))\n+ def gen_zero(self, f):\n+ f.write(code_fmt(f\"\"\"\\\n+ tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()},\n+ sizeof(MMQReg), sizeof(MMQReg), 0);\n+ \"\"\"))\n def gen_write(self, f, tag):\n pass\n def helper_hvx_desc(self, f):\n","prefixes":["v2","03/16"]}