{"id":2219024,"url":"http://patchwork.ozlabs.org/api/patches/2219024/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260402095107.205439-7-sherry.sun@nxp.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260402095107.205439-7-sherry.sun@nxp.com>","list_archive_url":null,"date":"2026-04-02T09:51:00","name":"[V10,06/13] arm: dts: imx6qdl: Add Root Port node and PERST property","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"43d7f52975a094b5879c870d0f333050853286c7","submitter":{"id":77063,"url":"http://patchwork.ozlabs.org/api/people/77063/?format=json","name":"Sherry Sun","email":"sherry.sun@nxp.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260402095107.205439-7-sherry.sun@nxp.com/mbox/","series":[{"id":498458,"url":"http://patchwork.ozlabs.org/api/series/498458/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=498458","date":"2026-04-02T09:50:55","name":"pci-imx6: Add support for parsing the reset property in new Root Port binding","version":10,"mbox":"http://patchwork.ozlabs.org/series/498458/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2219024/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2219024/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nxp.com header.i=@nxp.com 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","To":"robh@kernel.org,\n\tkrzk+dt@kernel.org,\n\tconor+dt@kernel.org,\n\tFrank.Li@nxp.com,\n\ts.hauer@pengutronix.de,\n\tkernel@pengutronix.de,\n\tfestevam@gmail.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\tbhelgaas@google.com,\n\thongxing.zhu@nxp.com,\n\tl.stach@pengutronix.de","Cc":"imx@lists.linux.dev,\n\tlinux-pci@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org","Subject":"[PATCH V10 06/13] arm: dts: imx6qdl: Add Root Port node and PERST\n property","Date":"Thu, 2 Apr 2026 17:51:00 +0800","Message-Id":"<20260402095107.205439-7-sherry.sun@nxp.com>","X-Mailer":"git-send-email 2.37.1","In-Reply-To":"<20260402095107.205439-1-sherry.sun@nxp.com>","References":"<20260402095107.205439-1-sherry.sun@nxp.com>","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-ClientProxiedBy":"MA5P287CA0163.INDP287.PROD.OUTLOOK.COM\n (2603:1096:a01:1ba::11) To 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bog20DJBPiHXcvrH/mA+UNQ0ZQkfy1RX29Z8jpJHlSpcgHh+/AKv7eUFGvCKQ0gg8I5ofoflq6oqDeG/e2VF6hhLtnmhk/myND4JqYkTPG72U863d97ByAKsb8Eei1HP7BEidAyRIch583I6BoMjp7aZY0TKr7tCJDD/d99gAFo1wM+N7AVZk26twSIabfjpmRfCKpO1Nnj5AnvwN5IcoIrG9tKmOv3aZ3ocro6Osejccer2LwnJs233ycG2kEHf9PPlx1LRYY6jXZlrcVlsNGv9jAw3H4YJkoFgc+iDNyUkFBAuH6EsTmZK2e5AAUtWHjycdk1WahwGwujbdy1d3DL6lkM10xDMvLVOsHzsz1i34pkeNyTkaCxnnL5ER8B7u1r2YHgLavRgDN9A7PT90ByUH4gKkca/1GoXgBTTQ1gLCzphAiqhTjJjDtl2qrgT/f/86JMOeZddC9pWttFeS9okYT+CMcmyBh2GoDrGuJmiJFR2GafD65dUJVPhmS+eoj0habBzY5mav3eRCVGPx4YOc97FfjiVaf5/hjmcAFvR92Ttm7UludBoES/85f8maFO4cl1TQ/UTZIALYaUTYk3Ay8iQ++CNSOFUARID4mgveFGlmTFxNom7+b7zrDErMZoopMCIXxQjLdUhbIJw6W+S6eBFpjXBTk5VnMgrhX3MThsF5BIVbaSrPitB8URK001cu9PcW6valu5d3t5vPuFX9vrrYtnnXr76/weWilPbDt8OFgupR0LrZeim9Z9AqDTCcHzFK8B6FjmLpR13euof0w+S3gahCCrqN08HytFdPIrJ60VxArbxdnzN8wRjCJ05L2Uz2BMvk/F0+0qsYPRr79/O+koKpHA1WMFhYPvcoiWXD8YlQxpaIYxrBM6Y79ruBSQmQGEX2TzkLIaHFO5yzFnDeOne+BBU7BiJz54xMVAfZbLq1jQhcFk1lYWd7fFF1ik8lVyo8+Z4L/+fQo6CMOBydBJyayP5cE6MYL7kS83pXvrpVmUOU7FLfZsk/c0TxVTJ3wg8WLoRljkrh74ypS/BuBSOqlmS/GUIx7GyAD4JUilt275hoilOBgEkP83V0Uo+Z+fa6VXUezU/bbsjIg5xQcDMDWRxQiiUGJFEHpoLwHahNZ5v5x9N+kJT8dKpC+96MLMxiO0p5R2KuuuhcCiCjxiPuIDsOHerg057s8RA70dhUDy1yX/JfAi5KnHa0NqzNCivV5I4Jr5FAyOikfyDhQX6NEdRIIf7+yrM3mUXi+erT7bg2mJS3PKaZZG60H17qywYL5s5Ao1F+DTjVcrvv3GT00euUlRhRvK4cLnIH6LB2eSomhpoRy9+O5ThDSvnwAeuBnTCY4xMtN6bISNb1QVbQJuJY8qHJhd6UFKgcokFGgX3ZehgRQHLE7DcPTO0fwAXhyE5Fo4kZWz+F2OkNm7vlwOzVvIrVyjECUo1nTVQR1xRp+rORIKYD0bSYPq+SHWeuN64s+un28MOQ/zNWU55DXAC3PCGbDSziRFlMQexateAWBCdV/Xv03cXXjF00Fno52GK5llO44b/Q911htjQvcxARyIKz6OTqs4cxxCcGk2TjN0xxbKylAnzE38v4arF5jEXsOD/na3xVQvlCn9G2yB1kCVIQgT5QtU2AY+3hchHodWzbBR/HlYO1Nf1eTpCOGNxBhJW4UIjiRCqbjLtlFZxEJAEktI4HR1IXg1sudPYbAGOomBz3Xgn4p02B+WXYiN9ENAWTQ==","X-OriginatorOrg":"nxp.com","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 65c36a04-dca8-4aa2-5f28-08de909d4bbb","X-MS-Exchange-CrossTenant-AuthSource":"VI0PR04MB12114.eurprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"02 Apr 2026 09:50:39.2023\n (UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"686ea1d3-bc2b-4c6f-a92c-d99c5c301635","X-MS-Exchange-CrossTenant-MailboxType":"HOSTED","X-MS-Exchange-CrossTenant-UserPrincipalName":"\n riw0U7HbZKDMUX7Gu+cwfdpv4WF47ZcniqlMNkR5pz6fBJSVLP/FCoFhrBXi+N+8yg6AA8qpYN1fQvDMAmiY6Q==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"AM9PR04MB8471"},"content":"Since describing the PCIe PERST# property under Host Bridge node is now\ndeprecated, it is recommended to add it to the Root Port node, so\ncreating the Root Port node and add the reset-gpios property in Root\nPort.\n\nSigned-off-by: Sherry Sun \n---\n arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi | 5 +++++\n arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi | 11 +++++++++++\n arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts | 5 +++++\n 3 files changed, 21 insertions(+)","diff":"diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi\nindex ba29720e3f72..fe9046c03ddd 100644\n--- a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi\n+++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi\n@@ -754,11 +754,16 @@ lvds0_out: endpoint {\n &pcie {\n \tpinctrl-names = \"default\";\n \tpinctrl-0 = <&pinctrl_pcie>;\n+\t/* This property is deprecated, use reset-gpios from the Root Port node. */\n \treset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;\n \tvpcie-supply = <®_pcie>;\n \tstatus = \"okay\";\n };\n \n+&pcie_port0 {\n+\treset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;\n+};\n+\n &pwm1 {\n \tpinctrl-names = \"default\";\n \tpinctrl-0 = <&pinctrl_pwm1>;\ndiff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi\nindex 4dc2c410cf61..9438862b9927 100644\n--- a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi\n+++ b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi\n@@ -302,6 +302,17 @@ pcie: pcie@1ffc000 {\n \t\t\t\t <&clks IMX6QDL_CLK_PCIE_REF_125M>;\n \t\t\tclock-names = \"pcie\", \"pcie_bus\", \"pcie_phy\";\n \t\t\tstatus = \"disabled\";\n+\n+\t\t\tpcie_port0: pcie@0 {\n+\t\t\t\tcompatible = \"pciclass,0604\";\n+\t\t\t\tdevice_type = \"pci\";\n+\t\t\t\treg = <0x0 0x0 0x0 0x0 0x0>;\n+\t\t\t\tbus-range = <0x01 0xff>;\n+\n+\t\t\t\t#address-cells = <3>;\n+\t\t\t\t#size-cells = <2>;\n+\t\t\t\tranges;\n+\t\t\t};\n \t\t};\n \n \t\taips1: bus@2000000 { /* AIPS1 */\ndiff --git a/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts\nindex c5b220aeaefd..6b12cab7175f 100644\n--- a/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts\n+++ b/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts\n@@ -45,10 +45,15 @@ MX6QDL_PAD_GPIO_6__ENET_IRQ\t\t0x000b1\n };\n \n &pcie {\n+\t/* This property is deprecated, use reset-gpios from the Root Port node. */\n \treset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>;\n \tstatus = \"okay\";\n };\n \n+&pcie_port0 {\n+\treset-gpios = <&max7310_c 5 GPIO_ACTIVE_LOW>;\n+};\n+\n &sata {\n \tstatus = \"okay\";\n };\n","prefixes":["V10","06/13"]}