{"id":2219019,"url":"http://patchwork.ozlabs.org/api/patches/2219019/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260402095107.205439-13-sherry.sun@nxp.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260402095107.205439-13-sherry.sun@nxp.com>","list_archive_url":null,"date":"2026-04-02T09:51:06","name":"[V10,12/13] arm64: dts: imx8dxl/qm/qxp: Add Root Port node and PERST property","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"abba5f1ba9856206e772e59eeef6d23581b4ea95","submitter":{"id":77063,"url":"http://patchwork.ozlabs.org/api/people/77063/?format=json","name":"Sherry Sun","email":"sherry.sun@nxp.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260402095107.205439-13-sherry.sun@nxp.com/mbox/","series":[{"id":498458,"url":"http://patchwork.ozlabs.org/api/series/498458/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=498458","date":"2026-04-02T09:50:55","name":"pci-imx6: Add support for parsing the reset property in new Root Port binding","version":10,"mbox":"http://patchwork.ozlabs.org/series/498458/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2219019/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2219019/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nxp.com header.i=@nxp.com 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","To":"robh@kernel.org,\n\tkrzk+dt@kernel.org,\n\tconor+dt@kernel.org,\n\tFrank.Li@nxp.com,\n\ts.hauer@pengutronix.de,\n\tkernel@pengutronix.de,\n\tfestevam@gmail.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\tbhelgaas@google.com,\n\thongxing.zhu@nxp.com,\n\tl.stach@pengutronix.de","Cc":"imx@lists.linux.dev,\n\tlinux-pci@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org","Subject":"[PATCH V10 12/13] arm64: dts: imx8dxl/qm/qxp: Add Root Port node and\n PERST property","Date":"Thu, 2 Apr 2026 17:51:06 +0800","Message-Id":"<20260402095107.205439-13-sherry.sun@nxp.com>","X-Mailer":"git-send-email 2.37.1","In-Reply-To":"<20260402095107.205439-1-sherry.sun@nxp.com>","References":"<20260402095107.205439-1-sherry.sun@nxp.com>","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-ClientProxiedBy":"MA5P287CA0163.INDP287.PROD.OUTLOOK.COM\n (2603:1096:a01:1ba::11) To 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Aw+8NtG2PTSSW5kuu+GBKM4FjtZzd/NLZC5QORf63+aQT54IIzJi26dmsMDwXMaHdlpHEwWe6cWOqnhaSYzhbQ+56UnJYhnOCF79qXlCM6B50Rsd75+P0vn+fJJFqwb5//Fxenov3n3MQQ20B/47rHTKIEshnqLQ4aNUneutU6NyN8pYsZlzUkm0V//592Vy28Zu3NYeqi6bChb57crrM7HYs/I0FaDVLESBobi/Mrbx6XUwMMnQpgwv2za4kMc/IlTTlGs3IA6GsC8XONP1zn92rt89dhjrDCeAT9RsrkXQ8NfEcTb8U7Eys0iWMMekQI7dqt8we7IH7eWgL2iWPpY4FLd1e6xxgeqv3WfA8TcRRXTDnzwnxe9c8yncQbsiUqhCvl5BKi1qCLxU/h2J+1u5VX0V1yDDBt70JPdQzq9JGfJSqP3StF6IKOOC+moU8OcvEtDHW4RZQIg5vBjbqxxV38gKkSa5iFFEJK7TeE3/dnQrzkVpQqH8mYN9RS+zlM4AssJ40u+tp8sczw5HTLdAMZwwny3AS69P0JpJ6oqTqcchSY1Yer4PG3oFIxHTTR/94gJpOylvRqxZ4DRAJA+GIwwjOj2JMEtD0N6nLfuVAPg6v4W6h/TyiTdWrN+xhFFR7QnGn+IdI1e90bl2OJ4lr3kILL/COJ0caZGUJ92Yro12z4mdEdkfNXhmFpsrv5BznImg70b94DVh2YStJmb+agp4j6OlzrbJnzcAmaqHMDhZlCfbd79k2hT6l2RKF2Q3Y9ti4AeMbpUgn9fVK8UcubmehIiAbrWT6nJOqrlnvaOfwf1DntnjbgLZSipT4IskYmYK745GMlkNoV9MVupRXzRLi45aGm+AJmjIwW8l0iMEQuwKU9B5DQq5ArM+JtQ9aM5bQIfv1xtqmuSh5Q9aEEuJjENIdBo/+xoIU+GAeIB2UP5foOSktoj0r8xyR+bMQ/RJ/zhnPFoa0h+5qet0A/R7BWZOMmXob5om5rMEcJ+23LEPzuSQR6cRCc//SsgerVopjyNt15JgPDCNuRk737K8NwDBseipTFDnUZt9kfavsT+wD7cZCgNDy7FLW0Sray4NFGUu1L5VLIm5uPumeSHXFKvXsX7mm2UVSqXelwOJDde24Wgh1quV0+To+BRPXgO+UIGNqxTTAVWOrsSo7YZwPJCW79cBBl/wBgOkoZRNxC7NEfvXgTOW5CN3C+jCMZu29OAKagPuwHZMmRHTCflSPzpcyAM0dMG0SZ5Y9ezJinFbjyUBnHdNaDks6Jm54C5759pxniWARvzMMJ3d9xT4KlYBtHGO2bptw++YFlPVgj0fKXc+9BVkcIpaYx9SvLv7IUTVlvfx/f46M8FOsRNdTfn4ZDhLOlKl8LUAGNSrDIYazBzow5xXSo3vsW9tftRARDoOGF7vcBi16qhOiclSUYqEzs2reA15Oc7T9CRuhy3ZNKP2ETZ2fPHopTPRnio9RBxM1EtQVxtlyv/U0KLRW2LjyZ5DyWR3DHg0k2jK62ASiSw0hmXosW5x8ah8WgNqp7qrQk2WvQGDn4+ljBg2YkiohUjAabs4BUJ3XBcPke0eiKqgMieyVENC7CXNh6SylaLsQGlwINoaYPpLPPXp2v88mo4zGGeeXF7Bt7ws9b5EwGQ5eiWmfnaQiy8XFjbyDmlI07Jjs9g6nUeZlteE24tfnRTWyrr0XYP9rNeSGwKrmFAuqhOpjIg3fQeQzooHhwPPWwJi8PGjqQ==","X-OriginatorOrg":"nxp.com","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n fb2c2d94-b12c-44ad-8d3f-08de909d623f","X-MS-Exchange-CrossTenant-AuthSource":"VI0PR04MB12114.eurprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"02 Apr 2026 09:51:16.8022\n (UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"686ea1d3-bc2b-4c6f-a92c-d99c5c301635","X-MS-Exchange-CrossTenant-MailboxType":"HOSTED","X-MS-Exchange-CrossTenant-UserPrincipalName":"\n TTdbfgKkW+VIEZMG7NaogXC3wtT+ljgNvsHh2PL1rzveiYfkCD8ygewsf7qWpN3Q8LID95aF62sjcT+K68oTwA==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"DB9PR04MB9865"},"content":"Since describing the PCIe PERST# property under Host Bridge node is now\ndeprecated, it is recommended to add it to the Root Port node, so\ncreating the Root Port node and add the reset-gpios property in Root\nPort.\n\nSigned-off-by: Sherry Sun \n---\n .../boot/dts/freescale/imx8-ss-hsio.dtsi | 11 ++++++++++\n arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 5 +++++\n arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 10 +++++++++\n .../boot/dts/freescale/imx8qm-ss-hsio.dtsi | 22 +++++++++++++++++++\n arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 5 +++++\n 5 files changed, 53 insertions(+)","diff":"diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi\nindex 469de8b536b5..009990b2e559 100644\n--- a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi\n+++ b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi\n@@ -78,6 +78,17 @@ pcieb: pcie@5f010000 {\n \t\tpower-domains = <&pd IMX_SC_R_PCIE_B>;\n \t\tfsl,max-link-speed = <3>;\n \t\tstatus = \"disabled\";\n+\n+\t\tpcieb_port0: pcie@0 {\n+\t\t\tcompatible = \"pciclass,0604\";\n+\t\t\tdevice_type = \"pci\";\n+\t\t\treg = <0x0 0x0 0x0 0x0 0x0>;\n+\t\t\tbus-range = <0x01 0xff>;\n+\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tranges;\n+\t\t};\n \t};\n \n \tpcieb_ep: pcie-ep@5f010000 {\ndiff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts\nindex bc62ae5ca812..39108a915f96 100644\n--- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts\n+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts\n@@ -675,6 +675,7 @@ &pcie0 {\n \tphy-names = \"pcie-phy\";\n \tpinctrl-0 = <&pinctrl_pcieb>;\n \tpinctrl-names = \"default\";\n+\t/* This property is deprecated, use reset-gpios from the Root Port node. */\n \treset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;\n \tvpcie-supply = <®_pcieb>;\n \tvpcie3v3aux-supply = <®_pcieb>;\n@@ -691,6 +692,10 @@ &pcie0_ep {\n \tstatus = \"disabled\";\n };\n \n+&pcieb_port0 {\n+\treset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;\n+};\n+\n &sai0 {\n \tpinctrl-names = \"default\";\n \tpinctrl-0 = <&pinctrl_sai0>;\ndiff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts\nindex 011a89d85961..f706c86137c0 100644\n--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts\n+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts\n@@ -810,6 +810,7 @@ &pciea {\n \tphy-names = \"pcie-phy\";\n \tpinctrl-0 = <&pinctrl_pciea>;\n \tpinctrl-names = \"default\";\n+\t/* This property is deprecated, use reset-gpios from the Root Port node. */\n \treset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>;\n \tvpcie-supply = <®_pciea>;\n \tvpcie3v3aux-supply = <®_pciea>;\n@@ -817,15 +818,24 @@ &pciea {\n \tstatus = \"okay\";\n };\n \n+&pciea_port0 {\n+\treset-gpios = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>;\n+};\n+\n &pcieb {\n \tphys = <&hsio_phy 1 PHY_TYPE_PCIE 1>;\n \tphy-names = \"pcie-phy\";\n \tpinctrl-0 = <&pinctrl_pcieb>;\n \tpinctrl-names = \"default\";\n+\t/* This property is deprecated, use reset-gpios from the Root Port node. */\n \treset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>;\n \tstatus = \"disabled\";\n };\n \n+&pcieb_port0 {\n+\treset-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>;\n+};\n+\n &qm_pwm_lvds0 {\n \tpinctrl-names = \"default\";\n \tpinctrl-0 = <&pinctrl_pwm_lvds0>;\ndiff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi\nindex f2c94cdb682b..2e4fbfe0ca16 100644\n--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi\n+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi\n@@ -41,6 +41,17 @@ pcie0: pciea: pcie@5f000000 {\n \t\tpower-domains = <&pd IMX_SC_R_PCIE_A>;\n \t\tfsl,max-link-speed = <3>;\n \t\tstatus = \"disabled\";\n+\n+\t\tpciea_port0: pcie@0 {\n+\t\t\tcompatible = \"pciclass,0604\";\n+\t\t\tdevice_type = \"pci\";\n+\t\t\treg = <0x0 0x0 0x0 0x0 0x0>;\n+\t\t\tbus-range = <0x01 0xff>;\n+\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tranges;\n+\t\t};\n \t};\n \n \tpcie0_ep: pciea_ep: pcie-ep@5f000000 {\n@@ -91,6 +102,17 @@ pcie1: pcieb: pcie@5f010000 {\n \t\tpower-domains = <&pd IMX_SC_R_PCIE_B>;\n \t\tfsl,max-link-speed = <3>;\n \t\tstatus = \"disabled\";\n+\n+\t\tpcieb_port0: pcie@0 {\n+\t\t\tcompatible = \"pciclass,0604\";\n+\t\t\tdevice_type = \"pci\";\n+\t\t\treg = <0x0 0x0 0x0 0x0 0x0>;\n+\t\t\tbus-range = <0x01 0xff>;\n+\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tranges;\n+\t\t};\n \t};\n \n \tsata: sata@5f020000 {\ndiff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts\nindex 623169f7ddb5..489e174df4c4 100644\n--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts\n+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts\n@@ -730,6 +730,7 @@ &pcie0 {\n \tphy-names = \"pcie-phy\";\n \tpinctrl-0 = <&pinctrl_pcieb>;\n \tpinctrl-names = \"default\";\n+\t/* This property is deprecated, use reset-gpios from the Root Port node. */\n \treset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;\n \tvpcie-supply = <®_pcieb>;\n \tvpcie3v3aux-supply = <®_pcieb>;\n@@ -746,6 +747,10 @@ &pcie0_ep {\n \tstatus = \"disabled\";\n };\n \n+&pcieb_port0 {\n+\treset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;\n+};\n+\n &scu_key {\n \tstatus = \"okay\";\n };\n","prefixes":["V10","12/13"]}