{"id":2219010,"url":"http://patchwork.ozlabs.org/api/patches/2219010/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260402095132.29245-10-thuth@redhat.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260402095132.29245-10-thuth@redhat.com>","list_archive_url":null,"date":"2026-04-02T09:51:31","name":"[09/10] target/i386: Support migrating from i386 to x86_64 target","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"e928e5b099e8cdaac28bb0d815f1a8b821d509fd","submitter":{"id":66152,"url":"http://patchwork.ozlabs.org/api/people/66152/?format=json","name":"Thomas Huth","email":"thuth@redhat.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260402095132.29245-10-thuth@redhat.com/mbox/","series":[{"id":498459,"url":"http://patchwork.ozlabs.org/api/series/498459/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498459","date":"2026-04-02T09:51:22","name":"Deprecate the qemu-system-i386 binary","version":1,"mbox":"http://patchwork.ozlabs.org/series/498459/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2219010/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2219010/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256\n header.s=mimecast20190719 header.b=cU+j3yFz;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fmcd50FkTz1yGH\n\tfor ; Thu, 02 Apr 2026 20:54:01 +1100 (AEDT)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1w8Eiy-00079b-6o; Thu, 02 Apr 2026 05:52:28 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from ) id 1w8Eiu-00078v-QK\n for qemu-devel@nongnu.org; Thu, 02 Apr 2026 05:52:24 -0400","from us-smtp-delivery-124.mimecast.com ([170.10.129.124])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from ) id 1w8Eis-0008TM-SP\n for qemu-devel@nongnu.org; Thu, 02 Apr 2026 05:52:24 -0400","from mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com\n (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by\n relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3,\n cipher=TLS_AES_256_GCM_SHA384) id us-mta-99-4uqSidACPHiJXw1hTNwhTg-1; Thu,\n 02 Apr 2026 05:52:17 -0400","from mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com\n (mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.17])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest\n SHA256)\n (No client certificate requested)\n by mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS\n id 00733180047F; Thu, 2 Apr 2026 09:52:16 +0000 (UTC)","from thuth-p1g4.redhat.com (unknown [10.44.34.44])\n by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP\n id 66333196B088; Thu, 2 Apr 2026 09:52:12 +0000 (UTC)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com;\n s=mimecast20190719; t=1775123540;\n h=from:from:reply-to:subject:subject:date:date:message-id:message-id:\n to:to:cc:cc:mime-version:mime-version:\n content-transfer-encoding:content-transfer-encoding:\n in-reply-to:in-reply-to:references:references;\n bh=1gBbz0lXmLXZQfWTPJ1x/oz786AusvxHAXLc6WW8Klk=;\n b=cU+j3yFzsVA5KzeyJqg7qlV/Rb9wd8AD6OWhfOd4ZBa4JSQ75sGjCS1+o7gZ8NgltvcA+q\n 1hz7lukx1lXXk343cDPe2+03IU+kBYBZSF1WB5M6xuaBLosPx/Eoi8knwwarafQI/yN5FF\n TABXk1IXX2yBFIUnGtDhRJZa+2nn7sk=","X-MC-Unique":"4uqSidACPHiJXw1hTNwhTg-1","X-Mimecast-MFC-AGG-ID":"4uqSidACPHiJXw1hTNwhTg_1775123536","From":"Thomas Huth ","To":"Paolo Bonzini ,\n\tqemu-devel@nongnu.org","Cc":"Pierrick Bouvier ,\n \"Michael S. Tsirkin\" ,\n Richard Henderson , =?utf-8?q?Philippe_Mathie?=\n\t=?utf-8?q?u-Daud=C3=A9?= , Zhao Liu ,\n Thomas Huth ","Subject":"[PATCH 09/10] target/i386: Support migrating from i386 to x86_64\n target","Date":"Thu, 2 Apr 2026 11:51:31 +0200","Message-ID":"<20260402095132.29245-10-thuth@redhat.com>","In-Reply-To":"<20260402095132.29245-1-thuth@redhat.com>","References":"<20260402095132.29245-1-thuth@redhat.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Scanned-By":"MIMEDefang 3.0 on 10.30.177.17","Received-SPF":"pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com;\n helo=us-smtp-delivery-124.mimecast.com","X-Spam_score_int":"-6","X-Spam_score":"-0.7","X-Spam_bar":"/","X-Spam_report":"(-0.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01,\n RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1, RCVD_IN_VALIDITY_RPBL_BLOCKED=1,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Thomas Huth \n\nFor migrating from qemu-system-i386 to qemu-system-x86_64, we have\nto support the CPU vmstate of the 32-bit target.\n\nSigned-off-by: Thomas Huth \n---\n target/i386/cpu.h | 47 +++++++--\n target/i386/cpu.c | 8 +-\n target/i386/machine.c | 222 ++++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 270 insertions(+), 7 deletions(-)","diff":"diff --git a/target/i386/cpu.h b/target/i386/cpu.h\nindex 78f2dadc2e3..88fcf44fdc0 100644\n--- a/target/i386/cpu.h\n+++ b/target/i386/cpu.h\n@@ -1632,6 +1632,13 @@ typedef struct SegmentCache {\n uint32_t flags;\n } SegmentCache;\n \n+typedef struct SegmentCache32 {\n+ uint32_t selector;\n+ uint32_t base;\n+ uint32_t limit;\n+ uint32_t flags;\n+} SegmentCache32;\n+\n typedef union MMXReg {\n uint8_t _b_MMXReg[64 / 8];\n uint16_t _w_MMXReg[64 / 16];\n@@ -1974,10 +1981,16 @@ typedef struct CPUCaches {\n typedef struct CPUArchState {\n /* standard registers */\n target_ulong regs[CPU_NB_EREGS];\n- target_ulong eip;\n- target_ulong eflags; /* eflags register. During CPU emulation, CC\n- flags and DF are set to zero because they are\n- stored elsewhere */\n+ union {\n+ target_ulong eip;\n+ uint32_t eip32;\n+ };\n+ union {\n+ target_ulong eflags; /* eflags register. During CPU emulation, CC\n+ flags and DF are set to zero because they are\n+ stored elsewhere */\n+ uint32_t eflags32;\n+ };\n \n /* emulator internal eflags handling */\n target_ulong cc_dst;\n@@ -2042,8 +2055,14 @@ typedef struct CPUArchState {\n \n /* sysenter registers */\n uint32_t sysenter_cs;\n- target_ulong sysenter_esp;\n- target_ulong sysenter_eip;\n+ union {\n+ target_ulong sysenter_esp;\n+ uint32_t sysenter_esp32;\n+ };\n+ union {\n+ target_ulong sysenter_eip;\n+ uint32_t sysenter_eip32;\n+ };\n uint64_t star;\n \n uint64_t vm_hsave;\n@@ -2294,6 +2313,21 @@ typedef struct CPUArchState {\n uint16_t fptag_vmstate;\n uint16_t fpregs_format_vmstate;\n \n+#ifdef TARGET_X86_64\n+ /*\n+ * These fields are only used for migrating from qemu-system-i386\n+ * to qemu-system-x86_64\n+ */\n+ uint32_t regs32[CPU_NB_REGS32];\n+ SegmentCache32 segs32[6]; /* selector values */\n+ SegmentCache32 ldt32;\n+ SegmentCache32 tr32;\n+ SegmentCache32 gdt32; /* only base and limit are used */\n+ SegmentCache32 idt32; /* only base and limit are used */\n+ uint32_t cr32[5];\n+ uint32_t dr32[8];\n+#endif\n+\n uint64_t xss;\n uint32_t umwait;\n \n@@ -2546,6 +2580,7 @@ struct X86CPUClass {\n \n #ifndef CONFIG_USER_ONLY\n extern const VMStateDescription vmstate_x86_cpu;\n+extern const VMStateDescription vmstate_i386_cpu;\n #endif\n \n int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,\ndiff --git a/target/i386/cpu.c b/target/i386/cpu.c\nindex a8ff1b29f33..a087a45dbfe 100644\n--- a/target/i386/cpu.c\n+++ b/target/i386/cpu.c\n@@ -10701,7 +10701,7 @@ static const Property x86_cpu_properties[] = {\n #ifndef CONFIG_USER_ONLY\n #include \"hw/core/sysemu-cpu-ops.h\"\n \n-static const struct SysemuCPUOps i386_sysemu_ops = {\n+static struct SysemuCPUOps i386_sysemu_ops = {\n .has_work = x86_cpu_has_work,\n .get_memory_mapping = x86_cpu_get_memory_mapping,\n .get_paging_enabled = x86_cpu_get_paging_enabled,\n@@ -10746,8 +10746,14 @@ static void x86_cpu_common_class_init(ObjectClass *oc, const void *data)\n \n #ifndef CONFIG_USER_ONLY\n cc->max_as = X86ASIdx_MAX;\n+#ifdef TARGET_X86_64\n+ if (target_i386()) {\n+ i386_sysemu_ops.legacy_vmsd = &vmstate_i386_cpu;\n+ }\n+#endif\n cc->sysemu_ops = &i386_sysemu_ops;\n #endif /* !CONFIG_USER_ONLY */\n+\n #ifdef CONFIG_TCG\n cc->tcg_ops = &x86_tcg_ops;\n #endif /* CONFIG_TCG */\ndiff --git a/target/i386/machine.c b/target/i386/machine.c\nindex 48a2a4b3190..bb6019d3419 100644\n--- a/target/i386/machine.c\n+++ b/target/i386/machine.c\n@@ -310,6 +310,44 @@ static int cpu_pre_save(void *opaque)\n return 0;\n }\n \n+\n+#ifdef TARGET_X86_64\n+static void copy_segcache(SegmentCache32 *sc32, SegmentCache *sc64)\n+{\n+ sc64->selector = sc32->selector;\n+ sc64->base = sc32->base;\n+ sc64->limit = sc32->limit;\n+ sc64->flags = sc32->flags;\n+}\n+#endif\n+\n+static void cpu_post_load_fixup32(CPUX86State *env)\n+{\n+#ifdef TARGET_X86_64\n+ int i;\n+\n+ for (i = 0; i < CPU_NB_REGS32; i++) {\n+ env->regs[i] = env->regs32[i];\n+ }\n+\n+ for (i = 0; i < ARRAY_SIZE(env->segs); i++) {\n+ copy_segcache(&env->segs32[i], &env->segs[i]);\n+ }\n+\n+ copy_segcache(&env->ldt32, &env->ldt);\n+ copy_segcache(&env->tr32, &env->tr);\n+ copy_segcache(&env->gdt32, &env->gdt);\n+ copy_segcache(&env->idt32, &env->idt);\n+\n+ for (i = 0; i < ARRAY_SIZE(env->cr); i++) {\n+ env->cr[i] = env->cr32[i];\n+ }\n+ for (i = 0; i < ARRAY_SIZE(env->dr); i++) {\n+ env->dr[i] = env->dr32[i];\n+ }\n+#endif\n+}\n+\n static int cpu_post_load(void *opaque, int version_id)\n {\n X86CPU *cpu = opaque;\n@@ -317,6 +355,10 @@ static int cpu_post_load(void *opaque, int version_id)\n CPUX86State *env = &cpu->env;\n int i;\n \n+ if (target_i386()) {\n+ cpu_post_load_fixup32(env);\n+ }\n+\n if (env->tsc_khz && env->user_tsc_khz &&\n env->tsc_khz != env->user_tsc_khz) {\n error_report(\"Mismatch between user-specified TSC frequency and \"\n@@ -1920,3 +1962,183 @@ const VMStateDescription vmstate_x86_cpu = {\n NULL\n }\n };\n+\n+/* ***************** 32-bit target hacks below **************** */\n+\n+#ifdef TARGET_X86_64\n+\n+static const VMStateDescription vmstate_segment32 = {\n+ .name = \"segment\",\n+ .version_id = 1,\n+ .minimum_version_id = 1,\n+ .fields = (const VMStateField[]) {\n+ VMSTATE_UINT32(selector, SegmentCache32),\n+ VMSTATE_UINT32(base, SegmentCache32),\n+ VMSTATE_UINT32(limit, SegmentCache32),\n+ VMSTATE_UINT32(flags, SegmentCache32),\n+ VMSTATE_END_OF_LIST()\n+ }\n+};\n+\n+#define VMSTATE_SEGMENT32(_field, _state) { \\\n+ .name = (stringify(_field)), \\\n+ .size = sizeof(SegmentCache32), \\\n+ .vmsd = &vmstate_segment32, \\\n+ .flags = VMS_STRUCT, \\\n+ .offset = offsetof(_state, _field) \\\n+ + type_check(SegmentCache32, typeof_field(_state, _field)) \\\n+}\n+\n+#define VMSTATE_SEGMENT32_ARRAY(_field, _state, _n) \\\n+ VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_segment32, SegmentCache32)\n+\n+#define VMSTATE_XMM32_REGS(_field, _state, _start) \\\n+ VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS32, 0, \\\n+ vmstate_xmm_reg, ZMMReg)\n+\n+#define VMSTATE_YMMH32_REGS_VARS(_field, _state, _start, _v) \\\n+ VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS32, _v, \\\n+ vmstate_ymmh_reg, ZMMReg)\n+\n+const VMStateDescription vmstate_i386_cpu = {\n+ .name = \"cpu\",\n+ .version_id = 12,\n+ .minimum_version_id = 11,\n+ .pre_save = cpu_pre_save,\n+ .post_load = cpu_post_load,\n+ .fields = (const VMStateField[]) {\n+ VMSTATE_UINT32_SUB_ARRAY(env.regs32, X86CPU, 0, CPU_NB_REGS32),\n+ VMSTATE_UINT32(env.eip32, X86CPU),\n+ VMSTATE_UINT32(env.eflags32, X86CPU),\n+ VMSTATE_UINT32(env.hflags, X86CPU),\n+ /* FPU */\n+ VMSTATE_UINT16(env.fpuc, X86CPU),\n+ VMSTATE_UINT16(env.fpus_vmstate, X86CPU),\n+ VMSTATE_UINT16(env.fptag_vmstate, X86CPU),\n+ VMSTATE_UINT16(env.fpregs_format_vmstate, X86CPU),\n+\n+ VMSTATE_STRUCT_ARRAY(env.fpregs, X86CPU, 8, 0, vmstate_fpreg, FPReg),\n+\n+ VMSTATE_SEGMENT32_ARRAY(env.segs32, X86CPU, 6),\n+ VMSTATE_SEGMENT32(env.ldt32, X86CPU),\n+ VMSTATE_SEGMENT32(env.tr32, X86CPU),\n+ VMSTATE_SEGMENT32(env.gdt32, X86CPU),\n+ VMSTATE_SEGMENT32(env.idt32, X86CPU),\n+\n+ VMSTATE_UINT32(env.sysenter_cs, X86CPU),\n+ VMSTATE_UINT32(env.sysenter_esp32, X86CPU),\n+ VMSTATE_UINT32(env.sysenter_eip32, X86CPU),\n+\n+ VMSTATE_UINT32(env.cr32[0], X86CPU),\n+ VMSTATE_UINT32(env.cr32[2], X86CPU),\n+ VMSTATE_UINT32(env.cr32[3], X86CPU),\n+ VMSTATE_UINT32(env.cr32[4], X86CPU),\n+ VMSTATE_UINT32_ARRAY(env.dr32, X86CPU, 8),\n+ /* MMU */\n+ VMSTATE_INT32(env.a20_mask, X86CPU),\n+ /* XMM */\n+ VMSTATE_UINT32(env.mxcsr, X86CPU),\n+ VMSTATE_XMM32_REGS(env.xmm_regs, X86CPU, 0),\n+\n+ VMSTATE_UINT32(env.smbase, X86CPU),\n+\n+ VMSTATE_UINT64(env.pat, X86CPU),\n+ VMSTATE_UINT32(env.hflags2, X86CPU),\n+\n+ VMSTATE_UINT64(env.vm_hsave, X86CPU),\n+ VMSTATE_UINT64(env.vm_vmcb, X86CPU),\n+ VMSTATE_UINT64(env.tsc_offset, X86CPU),\n+ VMSTATE_UINT64(env.intercept, X86CPU),\n+ VMSTATE_UINT16(env.intercept_cr_read, X86CPU),\n+ VMSTATE_UINT16(env.intercept_cr_write, X86CPU),\n+ VMSTATE_UINT16(env.intercept_dr_read, X86CPU),\n+ VMSTATE_UINT16(env.intercept_dr_write, X86CPU),\n+ VMSTATE_UINT32(env.intercept_exceptions, X86CPU),\n+ VMSTATE_UINT8(env.v_tpr, X86CPU),\n+ /* MTRRs */\n+ VMSTATE_UINT64_ARRAY(env.mtrr_fixed, X86CPU, 11),\n+ VMSTATE_UINT64(env.mtrr_deftype, X86CPU),\n+ VMSTATE_MTRR_VARS(env.mtrr_var, X86CPU, MSR_MTRRcap_VCNT, 8),\n+ /* KVM-related states */\n+ VMSTATE_INT32(env.interrupt_injected, X86CPU),\n+ VMSTATE_UINT32(env.mp_state, X86CPU),\n+ VMSTATE_UINT64(env.tsc, X86CPU),\n+ VMSTATE_INT32(env.exception_nr, X86CPU),\n+ VMSTATE_UINT8(env.soft_interrupt, X86CPU),\n+ VMSTATE_UINT8(env.nmi_injected, X86CPU),\n+ VMSTATE_UINT8(env.nmi_pending, X86CPU),\n+ VMSTATE_UINT8(env.has_error_code, X86CPU),\n+ VMSTATE_UINT32(env.sipi_vector, X86CPU),\n+ /* MCE */\n+ VMSTATE_UINT64(env.mcg_cap, X86CPU),\n+ VMSTATE_UINT64(env.mcg_status, X86CPU),\n+ VMSTATE_UINT64(env.mcg_ctl, X86CPU),\n+ VMSTATE_UINT64_ARRAY(env.mce_banks, X86CPU, MCE_BANKS_DEF * 4),\n+ /* rdtscp */\n+ VMSTATE_UINT64(env.tsc_aux, X86CPU),\n+ /* KVM pvclock msr */\n+ VMSTATE_UINT64(env.system_time_msr, X86CPU),\n+ VMSTATE_UINT64(env.wall_clock_msr, X86CPU),\n+ /* XSAVE related fields */\n+ VMSTATE_UINT64_V(env.xcr0, X86CPU, 12),\n+ VMSTATE_UINT64_V(env.xstate_bv, X86CPU, 12),\n+ VMSTATE_YMMH32_REGS_VARS(env.xmm_regs, X86CPU, 0, 12),\n+ VMSTATE_END_OF_LIST()\n+ /* The above list is not sorted /wrt version numbers, watch out! */\n+ },\n+ .subsections = (const VMStateDescription * const []) {\n+ &vmstate_exception_info,\n+ &vmstate_error_code,\n+ &vmstate_async_pf_msr,\n+ &vmstate_async_pf_int_msr,\n+ &vmstate_pv_eoi_msr,\n+ &vmstate_steal_time_msr,\n+ &vmstate_poll_control_msr,\n+ &vmstate_fpop_ip_dp,\n+ &vmstate_msr_tsc_adjust,\n+ &vmstate_msr_tscdeadline,\n+ &vmstate_msr_ia32_misc_enable,\n+ &vmstate_msr_ia32_feature_control,\n+ &vmstate_msr_architectural_pmu,\n+ &vmstate_mpx,\n+ &vmstate_msr_hyperv_hypercall,\n+ &vmstate_msr_hyperv_vapic,\n+ &vmstate_msr_hyperv_time,\n+ &vmstate_msr_hyperv_crash,\n+ &vmstate_msr_hyperv_runtime,\n+ &vmstate_msr_hyperv_synic,\n+ &vmstate_msr_hyperv_stimer,\n+ &vmstate_msr_hyperv_reenlightenment,\n+ &vmstate_avx512,\n+ &vmstate_xss,\n+ &vmstate_umwait,\n+ &vmstate_tsc_khz,\n+ &vmstate_msr_smi_count,\n+ &vmstate_pkru,\n+ &vmstate_pkrs,\n+ &vmstate_spec_ctrl,\n+ &amd_tsc_scale_msr_ctrl,\n+ &vmstate_mcg_ext_ctl,\n+ &vmstate_msr_intel_pt,\n+ &vmstate_msr_virt_ssbd,\n+ &vmstate_svm_npt,\n+ &vmstate_svm_guest,\n+#ifdef CONFIG_KVM\n+ &vmstate_nested_state,\n+ &vmstate_xen_vcpu,\n+#endif\n+ &vmstate_msr_tsx_ctrl,\n+ &vmstate_msr_intel_sgx,\n+ &vmstate_pdptrs,\n+ &vmstate_msr_xfd,\n+ &vmstate_msr_hwcr,\n+ &vmstate_arch_lbr,\n+ &vmstate_triple_fault,\n+ &vmstate_pl0_ssp,\n+ &vmstate_cet,\n+\n+ NULL\n+ }\n+};\n+\n+#endif /* TARGET_X86_64 */\n","prefixes":["09/10"]}