{"id":2219005,"url":"http://patchwork.ozlabs.org/api/patches/2219005/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260402095132.29245-5-thuth@redhat.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260402095132.29245-5-thuth@redhat.com>","list_archive_url":null,"date":"2026-04-02T09:51:26","name":"[04/10] cpu: Add a way to detect 32-bit mode from argv0","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"327c1eb59d223ffe5a9725432c9b6a8099d3efc7","submitter":{"id":66152,"url":"http://patchwork.ozlabs.org/api/people/66152/?format=json","name":"Thomas Huth","email":"thuth@redhat.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260402095132.29245-5-thuth@redhat.com/mbox/","series":[{"id":498459,"url":"http://patchwork.ozlabs.org/api/series/498459/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498459","date":"2026-04-02T09:51:22","name":"Deprecate the qemu-system-i386 binary","version":1,"mbox":"http://patchwork.ozlabs.org/series/498459/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2219005/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2219005/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256\n header.s=mimecast20190719 header.b=LwfkUB5z;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fmccD2vvwz1yGH\n\tfor ; Thu, 02 Apr 2026 20:53:16 +1100 (AEDT)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1w8Eia-0006vf-1F; Thu, 02 Apr 2026 05:52:04 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from ) id 1w8EiY-0006vW-Ky\n for qemu-devel@nongnu.org; Thu, 02 Apr 2026 05:52:02 -0400","from us-smtp-delivery-124.mimecast.com ([170.10.133.124])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from ) id 1w8EiX-0008RS-BA\n for qemu-devel@nongnu.org; Thu, 02 Apr 2026 05:52:02 -0400","from mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com\n (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by\n relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3,\n cipher=TLS_AES_256_GCM_SHA384) id us-mta-408-BFZieF7GP8-DbkfgPZqHTQ-1; Thu,\n 02 Apr 2026 05:51:56 -0400","from mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com\n (mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.17])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest\n SHA256)\n (No client certificate requested)\n by mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS\n id C3F4618005BD; Thu, 2 Apr 2026 09:51:55 +0000 (UTC)","from thuth-p1g4.redhat.com (unknown [10.44.34.44])\n by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP\n id 1360C196B088; Thu, 2 Apr 2026 09:51:51 +0000 (UTC)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com;\n s=mimecast20190719; t=1775123520;\n h=from:from:reply-to:subject:subject:date:date:message-id:message-id:\n to:to:cc:cc:mime-version:mime-version:\n content-transfer-encoding:content-transfer-encoding:\n in-reply-to:in-reply-to:references:references;\n bh=qIToqHE3DYdE6OROkXm1aZvJg+93ZnbgMttNmMm5Ihs=;\n b=LwfkUB5zjDgTVaF4ePdBgggVyo8rTYJALKQHLJXzhEngR+oxGUK0M/y0xBnLA1wZIjG3a9\n uPTlQPMZUiEymMGSjqOdV7bvOSl+zfltWr8WWD7mEQ/wDou83U+NeewShCFlMdxUFTRtce\n UbsPjxJX/gk0NO1huhp9s5ha/0DO9ls=","X-MC-Unique":"BFZieF7GP8-DbkfgPZqHTQ-1","X-Mimecast-MFC-AGG-ID":"BFZieF7GP8-DbkfgPZqHTQ_1775123515","From":"Thomas Huth ","To":"Paolo Bonzini ,\n\tqemu-devel@nongnu.org","Cc":"Pierrick Bouvier ,\n \"Michael S. Tsirkin\" ,\n Richard Henderson , =?utf-8?q?Philippe_Mathie?=\n\t=?utf-8?q?u-Daud=C3=A9?= , Zhao Liu ,\n Thomas Huth ","Subject":"[PATCH 04/10] cpu: Add a way to detect 32-bit mode from argv0","Date":"Thu, 2 Apr 2026 11:51:26 +0200","Message-ID":"<20260402095132.29245-5-thuth@redhat.com>","In-Reply-To":"<20260402095132.29245-1-thuth@redhat.com>","References":"<20260402095132.29245-1-thuth@redhat.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Scanned-By":"MIMEDefang 3.0 on 10.30.177.17","Received-SPF":"pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com;\n helo=us-smtp-delivery-124.mimecast.com","X-Spam_score_int":"-6","X-Spam_score":"-0.7","X-Spam_bar":"/","X-Spam_report":"(-0.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.01,\n RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1, RCVD_IN_VALIDITY_RPBL_BLOCKED=1,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Thomas Huth \n\nIn the future, we might want to avoid compiling certain targets separately\nfor 32-bit mode (i.e. -i386, -arm and -ppc) where the 64-bit variant is a\nsuperset of the 32-bit variant. But it would be good to provide a way to\nmimic the 32-bit behavior via the program name in case the users need this\ncompatibility for some scenarios. Thus add a function that checks\nfor the old 32-bit program names and sets a flag accordingly.\n\nSigned-off-by: Thomas Huth \n---\n include/qemu/target-info.h | 7 +++++++\n system/vl.c | 1 +\n target-info.c | 20 ++++++++++++++++++--\n 3 files changed, 26 insertions(+), 2 deletions(-)","diff":"diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h\nindex 0713ab4bb16..aa9b2e9b0cf 100644\n--- a/include/qemu/target-info.h\n+++ b/include/qemu/target-info.h\n@@ -9,6 +9,13 @@\n #ifndef QEMU_TARGET_INFO_H\n #define QEMU_TARGET_INFO_H\n \n+/**\n+ * target_info_adjust:\n+ *\n+ * Returns: Adjust the target according to the binary name of the executable.\n+ */\n+void target_info_adjust(const char *argv0);\n+\n /**\n * target_name:\n *\ndiff --git a/system/vl.c b/system/vl.c\nindex 246623b3196..45c9f5d5c7a 100644\n--- a/system/vl.c\n+++ b/system/vl.c\n@@ -2884,6 +2884,7 @@ void qemu_init(int argc, char **argv)\n \n error_init(argv[0]);\n qemu_init_exec_dir(argv[0]);\n+ target_info_adjust(argv[0]);\n \n os_setup_limits();\n \ndiff --git a/target-info.c b/target-info.c\nindex dea73b5fbca..b18fd4e0060 100644\n--- a/target-info.c\n+++ b/target-info.c\n@@ -12,6 +12,21 @@\n #include \"qemu/target-info-impl.h\"\n #include \"qapi/error.h\"\n \n+static bool force_32bit;\n+\n+void target_info_adjust(const char *argv0)\n+{\n+ switch (target_arch()) {\n+ case SYS_EMU_TARGET_X86_64:\n+ if (g_str_has_suffix(argv0, \"-i386\")) {\n+ force_32bit = true;\n+ }\n+ break;\n+ default:\n+ break;\n+ }\n+}\n+\n const char *target_name(void)\n {\n return target_info()->target_name;\n@@ -107,10 +122,11 @@ bool target_base_x86(void)\n \n bool target_i386(void)\n {\n- return target_arch() == SYS_EMU_TARGET_I386;\n+ return target_arch() == SYS_EMU_TARGET_I386 ||\n+ (target_arch() == SYS_EMU_TARGET_X86_64 && force_32bit);\n }\n \n bool target_x86_64(void)\n {\n- return target_arch() == SYS_EMU_TARGET_X86_64;\n+ return target_arch() == SYS_EMU_TARGET_X86_64 && !force_32bit;\n }\n","prefixes":["04/10"]}