{"id":2219000,"url":"http://patchwork.ozlabs.org/api/patches/2219000/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260402095132.29245-3-thuth@redhat.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260402095132.29245-3-thuth@redhat.com>","list_archive_url":null,"date":"2026-04-02T09:51:24","name":"[02/10] target/i386/tcg/sysemu: Allow 32-bit SMM code to be used in the 64-bit binary","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"93fa5f95b14d3b229c7ebb9c13abb2da27bdfb8c","submitter":{"id":66152,"url":"http://patchwork.ozlabs.org/api/people/66152/?format=json","name":"Thomas Huth","email":"thuth@redhat.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260402095132.29245-3-thuth@redhat.com/mbox/","series":[{"id":498459,"url":"http://patchwork.ozlabs.org/api/series/498459/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498459","date":"2026-04-02T09:51:22","name":"Deprecate the qemu-system-i386 binary","version":1,"mbox":"http://patchwork.ozlabs.org/series/498459/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2219000/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2219000/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256\n header.s=mimecast20190719 header.b=T2Qz7Glk;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fmcb36DJrz1yGH\n\tfor ; Thu, 02 Apr 2026 20:52:15 +1100 (AEDT)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1w8EiQ-0006uG-A4; Thu, 02 Apr 2026 05:51:54 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from ) id 1w8EiO-0006tr-M0\n for qemu-devel@nongnu.org; Thu, 02 Apr 2026 05:51:52 -0400","from us-smtp-delivery-124.mimecast.com ([170.10.129.124])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from ) id 1w8EiM-0008QM-Rl\n for qemu-devel@nongnu.org; Thu, 02 Apr 2026 05:51:52 -0400","from mx-prod-mc-03.mail-002.prod.us-west-2.aws.redhat.com\n (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by\n relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3,\n cipher=TLS_AES_256_GCM_SHA384) id us-mta-677-Jy3nCGZGP4CMkyty9WW0EQ-1; Thu,\n 02 Apr 2026 05:51:49 -0400","from mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com\n (mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.17])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest\n SHA256)\n (No client certificate requested)\n by mx-prod-mc-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS\n id D327119560B4; Thu, 2 Apr 2026 09:51:47 +0000 (UTC)","from thuth-p1g4.redhat.com (unknown [10.44.34.44])\n by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP\n id 3F201196B088; Thu, 2 Apr 2026 09:51:45 +0000 (UTC)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com;\n s=mimecast20190719; t=1775123510;\n h=from:from:reply-to:subject:subject:date:date:message-id:message-id:\n to:to:cc:cc:mime-version:mime-version:\n content-transfer-encoding:content-transfer-encoding:\n in-reply-to:in-reply-to:references:references;\n bh=SdGyZXxwTYuvuSTrhC9NuPS6j2R9Ll8NKs9BQm1mdDs=;\n b=T2Qz7GlkMRycp47XE91inaz1dXRhSB2x40dDBHth/91FufPGjE6EnOpKOIxv4z3/CDiT+b\n RhM5e9vGZAdSO91crDLPDFzeRlJ7keznhX1Ysj8FR51A7y+vuXAeahGJdWu2/4QFnU/n6q\n /ViFRXCw4YGogya4vkXHxc1OgcgS9/k=","X-MC-Unique":"Jy3nCGZGP4CMkyty9WW0EQ-1","X-Mimecast-MFC-AGG-ID":"Jy3nCGZGP4CMkyty9WW0EQ_1775123508","From":"Thomas Huth ","To":"Paolo Bonzini ,\n\tqemu-devel@nongnu.org","Cc":"Pierrick Bouvier ,\n \"Michael S. Tsirkin\" ,\n Richard Henderson , =?utf-8?q?Philippe_Mathie?=\n\t=?utf-8?q?u-Daud=C3=A9?= , Zhao Liu ,\n Thomas Huth ","Subject":"[PATCH 02/10] target/i386/tcg/sysemu: Allow 32-bit SMM code to be\n used in the 64-bit binary","Date":"Thu, 2 Apr 2026 11:51:24 +0200","Message-ID":"<20260402095132.29245-3-thuth@redhat.com>","In-Reply-To":"<20260402095132.29245-1-thuth@redhat.com>","References":"<20260402095132.29245-1-thuth@redhat.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Scanned-By":"MIMEDefang 3.0 on 10.30.177.17","Received-SPF":"pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com;\n helo=us-smtp-delivery-124.mimecast.com","X-Spam_score_int":"27","X-Spam_score":"2.7","X-Spam_bar":"++","X-Spam_report":"(2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01,\n RCVD_IN_SBL_CSS=3.335, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Thomas Huth \n\nThis is a preparation for the QEMU universal binary where we might want\nto support both, the x86_64 and the i386 target, in one binary. Instead\nof using #ifdef TARGET_X86_64 here, check the LM bit to select the 32-bit\nor 64-bit code during runtime.\n\nSigned-off-by: Thomas Huth \n---\n target/i386/tcg/system/smm_helper.c | 65 +++++++++++++++++++----------\n 1 file changed, 43 insertions(+), 22 deletions(-)","diff":"diff --git a/target/i386/tcg/system/smm_helper.c b/target/i386/tcg/system/smm_helper.c\nindex 3be78cd53d3..4bbe18a86fb 100644\n--- a/target/i386/tcg/system/smm_helper.c\n+++ b/target/i386/tcg/system/smm_helper.c\n@@ -23,24 +23,15 @@\n #include \"exec/log.h\"\n #include \"tcg/helper-tcg.h\"\n \n-\n-/* SMM support */\n-\n-#ifdef TARGET_X86_64\n-#define SMM_REVISION_ID 0x00020064\n-#else\n-#define SMM_REVISION_ID 0x00020000\n-#endif\n-\n-static void sm_state_init(X86CPU *cpu)\n+static void sm_state_init_64(X86CPU *cpu)\n {\n+#ifdef TARGET_X86_64\n CPUX86State *env = &cpu->env;\n CPUState *cs = CPU(cpu);\n SegmentCache *dt;\n int i, offset;\n target_ulong sm_state = env->smbase + 0x8000;\n \n-#ifdef TARGET_X86_64\n for (i = 0; i < 6; i++) {\n dt = &env->segs[i];\n offset = 0x7e00 + i * 16;\n@@ -92,9 +83,21 @@ static void sm_state_init(X86CPU *cpu)\n x86_stq_phys(cs, sm_state + 0x7f50, env->cr[3]);\n x86_stl_phys(cs, sm_state + 0x7f58, env->cr[0]);\n \n- x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID);\n+ x86_stl_phys(cs, sm_state + 0x7efc, 0x00020064); /* SMM revision ID */\n x86_stl_phys(cs, sm_state + 0x7f00, env->smbase);\n #else\n+ g_assert_not_reached();\n+#endif\n+}\n+\n+static void sm_state_init_32(X86CPU *cpu)\n+{\n+ CPUX86State *env = &cpu->env;\n+ CPUState *cs = CPU(cpu);\n+ SegmentCache *dt;\n+ int i, offset;\n+ target_ulong sm_state = env->smbase + 0x8000;\n+\n x86_stl_phys(cs, sm_state + 0x7ffc, env->cr[0]);\n x86_stl_phys(cs, sm_state + 0x7ff8, env->cr[3]);\n x86_stl_phys(cs, sm_state + 0x7ff4, cpu_compute_eflags(env));\n@@ -140,9 +143,8 @@ static void sm_state_init(X86CPU *cpu)\n }\n x86_stl_phys(cs, sm_state + 0x7f14, env->cr[4]);\n \n- x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID);\n+ x86_stl_phys(cs, sm_state + 0x7efc, 0x00020000); /* SMM revision ID */\n x86_stl_phys(cs, sm_state + 0x7ef8, env->smbase);\n-#endif\n }\n \n void do_smm_enter(X86CPU *cpu)\n@@ -160,13 +162,15 @@ void do_smm_enter(X86CPU *cpu)\n env->hflags2 |= HF2_NMI_MASK;\n }\n \n- sm_state_init(cpu);\n+ if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {\n+ sm_state_init_64(cpu);\n+ cpu_load_efer(env, 0);\n+ } else {\n+ sm_state_init_32(cpu);\n+ }\n \n /* init SMM cpu state */\n \n-#ifdef TARGET_X86_64\n- cpu_load_efer(env, 0);\n-#endif\n cpu_load_eflags(env, 0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C |\n DF_MASK));\n env->eip = 0x00008000;\n@@ -197,15 +201,16 @@ void do_smm_enter(X86CPU *cpu)\n DESC_G_MASK | DESC_A_MASK);\n }\n \n-static void rsm_load_regs(CPUX86State *env)\n+static void rsm_load_regs_64(CPUX86State *env)\n {\n+#ifdef TARGET_X86_64\n CPUState *cs = env_cpu(env);\n target_ulong sm_state;\n int i, offset;\n uint32_t val;\n \n sm_state = env->smbase + 0x8000;\n-#ifdef TARGET_X86_64\n+\n cpu_load_efer(env, x86_ldq_phys(cs, sm_state + 0x7ed0));\n \n env->gdt.base = x86_ldq_phys(cs, sm_state + 0x7e68);\n@@ -260,6 +265,19 @@ static void rsm_load_regs(CPUX86State *env)\n env->smbase = x86_ldl_phys(cs, sm_state + 0x7f00);\n }\n #else\n+ g_assert_not_reached();\n+#endif\n+}\n+\n+static void rsm_load_regs_32(CPUX86State *env)\n+{\n+ CPUState *cs = env_cpu(env);\n+ target_ulong sm_state;\n+ int i, offset;\n+ uint32_t val;\n+\n+ sm_state = env->smbase + 0x8000;\n+\n cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7ffc));\n cpu_x86_update_cr3(env, x86_ldl_phys(cs, sm_state + 0x7ff8));\n cpu_load_eflags(env, x86_ldl_phys(cs, sm_state + 0x7ff4),\n@@ -312,14 +330,17 @@ static void rsm_load_regs(CPUX86State *env)\n if (val & 0x20000) {\n env->smbase = x86_ldl_phys(cs, sm_state + 0x7ef8);\n }\n-#endif\n }\n \n void helper_rsm(CPUX86State *env)\n {\n X86CPU *cpu = env_archcpu(env);\n \n- rsm_load_regs(env);\n+ if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {\n+ rsm_load_regs_64(env);\n+ } else {\n+ rsm_load_regs_32(env);\n+ }\n \n if ((env->hflags2 & HF2_SMM_INSIDE_NMI_MASK) == 0) {\n env->hflags2 &= ~HF2_NMI_MASK;\n","prefixes":["02/10"]}