{"id":2218998,"url":"http://patchwork.ozlabs.org/api/patches/2218998/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260402095107.205439-5-sherry.sun@nxp.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260402095107.205439-5-sherry.sun@nxp.com>","list_archive_url":null,"date":"2026-04-02T09:50:58","name":"[V10,04/13] PCI: imx6: Assert PERST# before enabling regulators","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"62d1ebc7c98301a0f45a12b0e2759bcf378331ba","submitter":{"id":77063,"url":"http://patchwork.ozlabs.org/api/people/77063/?format=json","name":"Sherry Sun","email":"sherry.sun@nxp.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260402095107.205439-5-sherry.sun@nxp.com/mbox/","series":[{"id":498458,"url":"http://patchwork.ozlabs.org/api/series/498458/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=498458","date":"2026-04-02T09:50:55","name":"pci-imx6: Add support for parsing the reset property in new Root Port binding","version":10,"mbox":"http://patchwork.ozlabs.org/series/498458/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2218998/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2218998/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nxp.com header.i=@nxp.com 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","To":"robh@kernel.org,\n\tkrzk+dt@kernel.org,\n\tconor+dt@kernel.org,\n\tFrank.Li@nxp.com,\n\ts.hauer@pengutronix.de,\n\tkernel@pengutronix.de,\n\tfestevam@gmail.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\tbhelgaas@google.com,\n\thongxing.zhu@nxp.com,\n\tl.stach@pengutronix.de","Cc":"imx@lists.linux.dev,\n\tlinux-pci@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org","Subject":"[PATCH V10 04/13] PCI: imx6: Assert PERST# before enabling regulators","Date":"Thu, 2 Apr 2026 17:50:58 +0800","Message-Id":"<20260402095107.205439-5-sherry.sun@nxp.com>","X-Mailer":"git-send-email 2.37.1","In-Reply-To":"<20260402095107.205439-1-sherry.sun@nxp.com>","References":"<20260402095107.205439-1-sherry.sun@nxp.com>","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-ClientProxiedBy":"MA5P287CA0163.INDP287.PROD.OUTLOOK.COM\n (2603:1096:a01:1ba::11) To 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JuaZ8FMGFsTmXb65XOIqsxygeNG2YfCismdC8bbVHTzQcYTr7Db/RW9rh9Iak/+y9R0ChWLvciWfVNq2ZJqcDlqZ90Lwj89eISgxcmyT2mvyLIRBerTy/lEvYBl3JhCD98y1L9jRQFScbwGqHXw7m2xALGrolWG8LSw+wzP76XnvjOQC9PbuRp76E7rZv1ITDq6JjMcth1GMRHLx2mDvWUOjz4ZJx3eHPuHJO7A5rFPv5Mvqh2yHfeNJk6Y0QMHQnViixQXz2bUiEFyKuhoIZPMOoW8NlR/yO9kM4OEu63+pO7e/mfTodIjJ6pyYouaLK9v5qrIsqqsA1/JXP0UrpKdDeQDjKYG4K0aglq71JkDKesOHLLGcTPdvvSbz5z20myKucKMozLjRhqmdw8BM5lJW1NFrqg/IsoLsE1bukzFPBc9vWYNVtOMcCgPAb9t3pQJDNs2+X0nTZMAmF8ySFAAziWSGsSeGgnIkW3H0c4eKMG0WA16ENGZjRSXoRVXW8kbZ4c3NrWRBwlA21WQ8A2ed1C6dYIMcr7wbKNsJSojzh5z5ECI+yvkLRWGFaxIK6IourNXsZae1c99U//IBSD24zQAE8gip5u1FWgQ2KAbtWZRrHqYy8Oda9twim7PN7X7BemMCjNxRNh22RTo55wZpRlmzC6uqY2vMnZ+TEI8Yejgup+Rxp4Uc5UBlbWCd/cPjKU9S6EtafFnxMkhfOvJsAoAbVgy0nt6NK2sA513ai722b+3PZcHBr4FK0QFs0AtFh7LTy0fr2TanAOwX3ie9blWHoPYqoVmKyx4iyCJJDST/m6hCd+yCC4kcmQedAR0x2XOZvIGbFyfcU6hKii9KLdIlyLtsrgEXftYue+hHGI0NCOpiz7LokbdXUfefQirHwYW0ZsJ9qOov8se2P5g8dETJM1Cn5eUkT3siCv1Fo6v5stCDc942zZsTTVskxuw330O6q7NV0xMhMCIPIuWLk+sHmSEj5ll3PFVPfM4ETtC/qLOR9XKb+MoEC3daJi698OXQCB0ySXLb1ROYD+fFLkc23JRIJusGlzKNSvBRa3fyAJnApPh15s+c+Oj3FuHnmOknyKz/sXXtGf44VLMB6gy0ukEt8WHaBHZId1l0+VyCljWSUybJ1YdzsuqMHqEx9HgOXrdHEn2Dc6yriu8eGILs52YLEfvl2r9dOMbLEI58B3Ov7wbhih6u+YjPK+qgSUsnHF8vNUpBUhqOa8sgcjnxZkKyPcDzyMv0ZWV9TOJ0FC6u21lEW96CIWhU/zd2F8JdvCK9QxlxtL+05ML2nSDjprYBfu7lWEHhw6v20MzfmO/LYxlJ7ApeCrGNQGQIesUc+xH+V2ip8SmAx8T7fefBs0os1tcTvP/jPCWX3uAYiIz3PZkcn6OfpZSD7wVqQ5+eio3t7j/cFnUCJlmGEJ3+humbGgNPN5IVXjUigTh/9XiAMxYuBNYOpok8CpJxlSf3xaVVe5kRolrOXbXy1WMfM43/R/Zj81ggf7uUL+7hnST+nZWIXeLmibK9GJWsCfUEnxv21Cse3i/JuF6yBB3rmqX8+NKt5Z/o8+zcRpfCc9cg9ofJKLfo0F49Bch3V/H5ODJrQd+z/9Q46llR84qRvVPX0dKMYVL56avJEeuPON5AxR5YjHljsNJ0o9H5CBQHyQjC+ajKG9WsLskc3yZxEYxYz0czOm20sLnoeteO1ns2gVjOXy3DiqiXk4np0J35LsBpjZdP41YTJQ==","X-OriginatorOrg":"nxp.com","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 41cf5e8a-8ebe-4eb0-bfd0-08de909d443b","X-MS-Exchange-CrossTenant-AuthSource":"VI0PR04MB12114.eurprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"02 Apr 2026 09:50:26.3211\n (UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"686ea1d3-bc2b-4c6f-a92c-d99c5c301635","X-MS-Exchange-CrossTenant-MailboxType":"HOSTED","X-MS-Exchange-CrossTenant-UserPrincipalName":"\n Ae9/P6rK3rhnn6WEezZ9jhZtN/wCcalg5Yeagwvc3HJN8b2lzDvh817b7Yrifz2sIEtjeD4FL9nVYURS4K9Z3g==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"AM9PR04MB8471"},"content":"According to the PCIe initialization requirements, PERST# signal should\nbe asserted before applying power to the PCIe device, and deasserted\nafter power and reference clock are stable.\n\nCurrently, the driver enables the vpcie3v3aux regulator in\nimx_pcie_probe() before PERST# is asserted in imx_pcie_host_init(),\nwhich violates the PCIe power sequencing requirements. However, there\nis no issue so far because PERST# is requested as GPIOD_OUT_HIGH in\nimx_pcie_probe(), which guarantees that PERST# is asserted before\nenabling the vpcie3v3aux regulator.\n\nThis is prepare for the upcoming changes that will parse the reset\nproperty using the new Root Port binding, which will use GPIOD_ASIS\nwhen requesting the reset GPIO. With GPIOD_ASIS, the GPIO state is not\nguaranteed, so explicit sequencing is required.\n\nFix the power sequencing by:\n1. Moving vpcie3v3aux regulator enable from probe to\n imx_pcie_host_init(), where it can be properly sequenced with PERST#.\n2. Moving imx_pcie_assert_perst() before regulator and clock enable to\n ensure correct ordering.\n\nThe vpcie3v3aux regulator is kept enabled for the entire PCIe controller\nlifecycle and automatically disabled on device removal via devm cleanup.\n\nSigned-off-by: Sherry Sun \n---\n drivers/pci/controller/dwc/pci-imx6.c | 49 +++++++++++++++++++++------\n 1 file changed, 39 insertions(+), 10 deletions(-)","diff":"diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c\nindex 45d70ae7e04f..948ffb75d122 100644\n--- a/drivers/pci/controller/dwc/pci-imx6.c\n+++ b/drivers/pci/controller/dwc/pci-imx6.c\n@@ -166,6 +166,8 @@ struct imx_pcie {\n \tu32\t\t\ttx_swing_full;\n \tu32\t\t\ttx_swing_low;\n \tstruct regulator\t*vpcie;\n+\tstruct regulator\t*vpcie_aux;\n+\tbool\t\t\tvpcie_aux_enabled;\n \tstruct regulator\t*vph;\n \tvoid __iomem\t\t*phy_base;\n \n@@ -1220,6 +1222,13 @@ static void imx_pcie_disable_device(struct pci_host_bridge *bridge,\n \timx_pcie_remove_lut(imx_pcie, pci_dev_id(pdev));\n }\n \n+static void imx_pcie_vpcie_aux_disable(void *data)\n+{\n+\tstruct regulator *vpcie_aux = data;\n+\n+\tregulator_disable(vpcie_aux);\n+}\n+\n static void imx_pcie_assert_perst(struct imx_pcie *imx_pcie, bool assert)\n {\n \tif (assert) {\n@@ -1240,6 +1249,24 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)\n \tstruct imx_pcie *imx_pcie = to_imx_pcie(pci);\n \tint ret;\n \n+\timx_pcie_assert_perst(imx_pcie, true);\n+\n+\t/* Keep 3.3Vaux supply enabled for the entire PCIe controller lifecycle */\n+\tif (imx_pcie->vpcie_aux && !imx_pcie->vpcie_aux_enabled) {\n+\t\tret = regulator_enable(imx_pcie->vpcie_aux);\n+\t\tif (ret) {\n+\t\t\tdev_err(dev, \"failed to enable vpcie_aux regulator: %d\\n\",\n+\t\t\t\tret);\n+\t\t\treturn ret;\n+\t\t}\n+\t\timx_pcie->vpcie_aux_enabled = true;\n+\n+\t\tret = devm_add_action_or_reset(dev, imx_pcie_vpcie_aux_disable,\n+\t\t\t\t\t imx_pcie->vpcie_aux);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n \tif (imx_pcie->vpcie) {\n \t\tret = regulator_enable(imx_pcie->vpcie);\n \t\tif (ret) {\n@@ -1249,25 +1276,24 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)\n \t\t}\n \t}\n \n+\tret = imx_pcie_clk_enable(imx_pcie);\n+\tif (ret) {\n+\t\tdev_err(dev, \"unable to enable pcie clocks: %d\\n\", ret);\n+\t\tgoto err_reg_disable;\n+\t}\n+\n \tif (pp->bridge && imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT)) {\n \t\tpp->bridge->enable_device = imx_pcie_enable_device;\n \t\tpp->bridge->disable_device = imx_pcie_disable_device;\n \t}\n \n \timx_pcie_assert_core_reset(imx_pcie);\n-\timx_pcie_assert_perst(imx_pcie, true);\n \n \tif (imx_pcie->drvdata->init_phy)\n \t\timx_pcie->drvdata->init_phy(imx_pcie);\n \n \timx_pcie_configure_type(imx_pcie);\n \n-\tret = imx_pcie_clk_enable(imx_pcie);\n-\tif (ret) {\n-\t\tdev_err(dev, \"unable to enable pcie clocks: %d\\n\", ret);\n-\t\tgoto err_reg_disable;\n-\t}\n-\n \tif (imx_pcie->phy) {\n \t\tret = phy_init(imx_pcie->phy);\n \t\tif (ret) {\n@@ -1780,9 +1806,12 @@ static int imx_pcie_probe(struct platform_device *pdev)\n \tof_property_read_u32(node, \"fsl,max-link-speed\", &pci->max_link_speed);\n \timx_pcie->supports_clkreq = of_property_read_bool(node, \"supports-clkreq\");\n \n-\tret = devm_regulator_get_enable_optional(&pdev->dev, \"vpcie3v3aux\");\n-\tif (ret < 0 && ret != -ENODEV)\n-\t\treturn dev_err_probe(dev, ret, \"failed to enable Vaux supply\\n\");\n+\timx_pcie->vpcie_aux = devm_regulator_get_optional(&pdev->dev, \"vpcie3v3aux\");\n+\tif (IS_ERR(imx_pcie->vpcie_aux)) {\n+\t\tif (PTR_ERR(imx_pcie->vpcie_aux) != -ENODEV)\n+\t\t\treturn PTR_ERR(imx_pcie->vpcie_aux);\n+\t\timx_pcie->vpcie_aux = NULL;\n+\t}\n \n \timx_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, \"vpcie\");\n \tif (IS_ERR(imx_pcie->vpcie)) {\n","prefixes":["V10","04/13"]}