{"id":2216053,"url":"http://patchwork.ozlabs.org/api/patches/2216053/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260325184259.366-8-alireza.sanaee@huawei.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260325184259.366-8-alireza.sanaee@huawei.com>","list_archive_url":null,"date":"2026-03-25T18:42:55","name":"[7/9] hw/cxl: Add release-time teardown for direct-mapped extents","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"5eeb9c298ce8ca879ae2e03ba060bc8a7df70451","submitter":{"id":90159,"url":"http://patchwork.ozlabs.org/api/people/90159/?format=json","name":"Alireza Sanaee","email":"alireza.sanaee@huawei.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260325184259.366-8-alireza.sanaee@huawei.com/mbox/","series":[{"id":497484,"url":"http://patchwork.ozlabs.org/api/series/497484/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497484","date":"2026-03-25T18:42:48","name":"Application Specific Tagged Memory Support in CXL Type 3 Devices","version":1,"mbox":"http://patchwork.ozlabs.org/series/497484/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2216053/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2216053/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":"legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Wed, 25 Mar 2026 14:47:02 -0400","from mail.maildlp.com (unknown [172.18.224.107])\n by frasgout.his.huawei.com (SkyGuard) with ESMTPS id 4fgwq31L7bzHnGdQ;\n Thu, 26 Mar 2026 02:46:23 +0800 (CST)","from dubpeml500005.china.huawei.com (unknown [7.214.145.207])\n by mail.maildlp.com (Postfix) with ESMTPS id F3DB240587;\n Thu, 26 Mar 2026 02:46:58 +0800 (CST)","from a2303103017.china.huawei.com (10.47.66.203) by\n dubpeml500005.china.huawei.com (7.214.145.207) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.1544.11; Wed, 25 Mar 2026 18:46:57 +0000"],"To":"","CC":", , ,\n , ,\n , , ,\n , , ,\n , ","Subject":"[PATCH 7/9] hw/cxl: Add release-time teardown for direct-mapped\n extents","Date":"Wed, 25 Mar 2026 18:42:55 +0000","Message-ID":"<20260325184259.366-8-alireza.sanaee@huawei.com>","X-Mailer":"git-send-email 2.51.0.windows.2","In-Reply-To":"<20260325184259.366-1-alireza.sanaee@huawei.com>","References":"<20260325184259.366-1-alireza.sanaee@huawei.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-Originating-IP":"[10.47.66.203]","X-ClientProxiedBy":"lhrpeml500011.china.huawei.com (7.191.174.215) To\n dubpeml500005.china.huawei.com (7.214.145.207)","Received-SPF":"pass client-ip=185.176.79.56;\n envelope-from=alireza.sanaee@huawei.com; helo=frasgout.his.huawei.com","X-Spam_score_int":"-41","X-Spam_score":"-4.2","X-Spam_bar":"----","X-Spam_report":"(-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Reply-to":"Alireza Sanaee ","From":"Alireza Sanaee via qemu development ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Consolidate teardown into the release path so all cleanup flows through a\nsingle place.\n\nWhen an extent is removed, tear down any direct alias tied to it and unmap\na lazy-mode tagged backend before dropping the extent record. Partial\nrelease of backend-backed extents is rejected, since those backends are\ntracked one-per-extent and cannot be split.\n\nSigned-off-by: Alireza Sanaee \n---\n hw/cxl/cxl-mailbox-utils.c | 103 +++++++++++++++++++++++++++++-------\n hw/mem/cxl_type3.c | 37 ++++++++++++-\n include/hw/cxl/cxl_device.h | 9 +++-\n 3 files changed, 126 insertions(+), 23 deletions(-)","diff":"diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c\nindex 4684c33ba1..9853740994 100644\n--- a/hw/cxl/cxl-mailbox-utils.c\n+++ b/hw/cxl/cxl-mailbox-utils.c\n@@ -3532,7 +3532,8 @@ void cxl_insert_extent_to_extent_list(CXLDCExtentList *list,\n uint8_t *tag,\n uint16_t shared_seq,\n int rid,\n- uint64_t offset)\n+ uint64_t offset,\n+ int direct_window_idx)\n {\n CXLDCExtent *extent;\n \n@@ -3547,6 +3548,7 @@ void cxl_insert_extent_to_extent_list(CXLDCExtentList *list,\n }\n extent->shared_seq = shared_seq;\n extent->rid = rid;\n+ extent->direct_window_idx = direct_window_idx;\n \n QTAILQ_INSERT_TAIL(list, extent, node);\n }\n@@ -3571,7 +3573,8 @@ CXLDCExtentGroup *cxl_insert_extent_to_extent_group(CXLDCExtentGroup *group,\n uint8_t *tag,\n uint16_t shared_seq,\n int rid,\n- uint64_t offset)\n+ uint64_t offset,\n+ int direct_window_idx)\n {\n if (!group) {\n group = g_new0(CXLDCExtentGroup, 1);\n@@ -3579,7 +3582,8 @@ CXLDCExtentGroup *cxl_insert_extent_to_extent_group(CXLDCExtentGroup *group,\n }\n cxl_insert_extent_to_extent_list(&group->list,\n host_mem, fw, dpa, len,\n- tag, shared_seq, rid, offset);\n+ tag, shared_seq, rid, offset,\n+ direct_window_idx);\n return group;\n }\n \n@@ -3695,6 +3699,25 @@ static bool cxl_extent_find_extent_detail(CXLDCExtentGroupList *list,\n return false;\n }\n \n+static void cxl_unmap_extent_backend(CXLDCExtent *ent)\n+{\n+ MemoryRegion *mr;\n+\n+ if (!ent->hm) {\n+ return;\n+ }\n+\n+ mr = host_memory_backend_get_memory(ent->hm);\n+ if (!mr) {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"Could not get memory region from host memory backend\\n\");\n+ return;\n+ }\n+\n+ memory_region_set_enabled(mr, false);\n+ host_memory_backend_set_mapped(ent->hm, false);\n+}\n+\n static CXLRetCode cxl_dcd_add_dyn_cap_rsp_dry_run(CXLType3Dev *ct3d,\n const CXLUpdateDCExtentListInPl *in)\n {\n@@ -3856,11 +3879,12 @@ static CXLRetCode cmd_dcd_add_dyn_cap_rsp(const struct cxl_cmd *cmd,\n \n cxl_insert_extent_to_extent_list(extent_list,\n hmb_dc, fw, dpa, len,\n- tag, 0, rid, offset);\n+ tag, 0, rid, offset, mr_idx);\n } else {\n cxl_insert_extent_to_extent_list(extent_list,\n NULL, NULL, dpa, len,\n- NULL, 0, -1, (uint64_t)-1);\n+ NULL, 0, -1,\n+ (uint64_t)-1, -1);\n }\n ct3d->dc.total_extent_count += 1;\n ct3d->dc.nr_extents_accepted += 1;\n@@ -3892,7 +3916,8 @@ static uint32_t copy_extent_list(CXLDCExtentList *dst,\n ent->hm, ent->fw,\n ent->start_dpa, ent->len,\n ent->tag, ent->shared_seq,\n- ent->rid, ent->offset);\n+ ent->rid, ent->offset,\n+ ent->direct_window_idx);\n cnt++;\n }\n return cnt;\n@@ -3900,6 +3925,7 @@ static uint32_t copy_extent_list(CXLDCExtentList *dst,\n \n static CXLRetCode cxl_dc_extent_release_dry_run(CXLType3Dev *ct3d,\n const CXLUpdateDCExtentListInPl *in, CXLDCExtentList *updated_list,\n+ CXLDCExtentList *updated_removed_list,\n uint32_t *updated_list_size)\n {\n CXLDCExtent *ent, *ent_next;\n@@ -3909,6 +3935,9 @@ static CXLRetCode cxl_dc_extent_release_dry_run(CXLType3Dev *ct3d,\n CXLRetCode ret = CXL_MBOX_SUCCESS;\n \n QTAILQ_INIT(updated_list);\n+ if (updated_removed_list) {\n+ QTAILQ_INIT(updated_removed_list);\n+ }\n copy_extent_list(updated_list, &ct3d->dc.extents);\n \n for (i = 0; i < in->num_entries_updated; i++) {\n@@ -3942,25 +3971,44 @@ static CXLRetCode cxl_dc_extent_release_dry_run(CXLType3Dev *ct3d,\n }\n len_done = ent_len - len1 - len2;\n \n+ /*\n+ * Tagged backends are mapped one-backend-per-extent.\n+ * Partial release would leave a backend-backed extent\n+ * behind without a clean backend lifecycle.\n+ */\n+ if (ent->hm && (len1 || len2)) {\n+ ret = CXL_MBOX_INVALID_INPUT;\n+ goto free_and_exit;\n+ }\n+\n+ /* Cannot split extents with direct window mapping */\n+ if (ent->direct_window_idx >= 0 && (len1 || len2)) {\n+ ret = CXL_MBOX_INVALID_INPUT;\n+ goto free_and_exit;\n+ }\n+\n+ if (updated_removed_list) {\n+ cxl_insert_extent_to_extent_list(\n+ updated_removed_list, ent->hm, ent->fw,\n+ ent->start_dpa, ent->len, ent->tag, ent->shared_seq,\n+ ent->rid, ent->offset, ent->direct_window_idx);\n+ }\n+\n cxl_remove_extent_from_extent_list(updated_list, ent);\n cnt_delta--;\n \n if (len1) {\n- cxl_insert_extent_to_extent_list(updated_list,\n- NULL, NULL,\n- ent_start_dpa, len1,\n- ent->tag, 0,\n- ent->rid,\n- ent->offset);\n+ cxl_insert_extent_to_extent_list(\n+ updated_list, NULL, NULL,\n+ ent_start_dpa, len1, ent->tag, 0,\n+ ent->rid, ent->offset, ent->direct_window_idx);\n cnt_delta++;\n }\n if (len2) {\n- cxl_insert_extent_to_extent_list(updated_list,\n- NULL, NULL,\n- dpa + len, len2,\n- ent->tag, 0,\n- ent->rid,\n- ent->offset);\n+ cxl_insert_extent_to_extent_list(\n+ updated_list, NULL, NULL,\n+ dpa + len, len2, ent->tag, 0,\n+ ent->rid, ent->offset, ent->direct_window_idx);\n cnt_delta++;\n }\n \n@@ -4002,6 +4050,7 @@ static CXLRetCode cmd_dcd_release_dyn_cap(const struct cxl_cmd *cmd,\n CXLUpdateDCExtentListInPl *in = (void *)payload_in;\n CXLType3Dev *ct3d = CXL_TYPE3(cci->d);\n CXLDCExtentList updated_list;\n+ CXLDCExtentList updated_removed_list;\n CXLDCExtent *ent, *ent_next;\n uint32_t updated_list_size;\n CXLRetCode ret;\n@@ -4025,11 +4074,26 @@ static CXLRetCode cmd_dcd_release_dyn_cap(const struct cxl_cmd *cmd,\n }\n \n ret = cxl_dc_extent_release_dry_run(ct3d, in, &updated_list,\n+ &updated_removed_list,\n &updated_list_size);\n if (ret != CXL_MBOX_SUCCESS) {\n return ret;\n }\n \n+ if (ct3d->direct_mr_enabled) {\n+ /* Remove memory alias for the removed extents */\n+ QTAILQ_FOREACH_SAFE(ent, &updated_removed_list, node, ent_next) {\n+ cxl_remove_memory_alias(ct3d, ent->fw, ent->direct_window_idx);\n+ cxl_unmap_extent_backend(ent);\n+ cxl_remove_extent_from_extent_list(&updated_removed_list, ent);\n+ }\n+ } else {\n+ QTAILQ_FOREACH_SAFE(ent, &updated_removed_list, node, ent_next) {\n+ cxl_unmap_extent_backend(ent);\n+ cxl_remove_extent_from_extent_list(&updated_removed_list, ent);\n+ }\n+ }\n+\n /*\n * If the dry run release passes, the returned updated_list will\n * be the updated extent list and we just need to clear the extents\n@@ -4438,7 +4502,7 @@ static CXLRetCode cmd_fm_initiate_dc_add(const struct cxl_cmd *cmd,\n ext->start_dpa,\n ext->len, ext->tag,\n ext->shared_seq, 0,\n- (uint64_t)-1);\n+ (uint64_t)-1, -1);\n }\n \n cxl_extent_group_list_insert_tail(&ct3d->dc.extents_pending, group);\n@@ -4520,6 +4584,7 @@ static CXLRetCode cmd_fm_initiate_dc_release(const struct cxl_cmd *cmd,\n rc = cxl_dc_extent_release_dry_run(ct3d,\n list,\n &updated_list,\n+ NULL,\n &updated_list_size);\n if (rc) {\n return rc;\ndiff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c\nindex e13826eb0b..6b73d58358 100644\n--- a/hw/mem/cxl_type3.c\n+++ b/hw/mem/cxl_type3.c\n@@ -2465,7 +2465,8 @@ static void qmp_cxl_process_dynamic_capacity_prescriptive(const char *path,\n extents[i].tag,\n extents[i].shared_seq,\n rid,\n- offset);\n+ offset,\n+ 0);\n } else {\n group = cxl_insert_extent_to_extent_group(group,\n dcd->dc.host_dc,\n@@ -2475,7 +2476,8 @@ static void qmp_cxl_process_dynamic_capacity_prescriptive(const char *path,\n extents[i].tag,\n extents[i].shared_seq,\n rid,\n- offset);\n+ offset,\n+ 0);\n }\n }\n \n@@ -2541,6 +2543,37 @@ void qmp_cxl_release_dynamic_capacity(const char *path, uint16_t host_id,\n }\n }\n \n+void cxl_remove_memory_alias(CXLType3Dev *dcd, struct CXLFixedWindow *fw,\n+ int hdm_id)\n+{\n+ MemoryRegion *mr;\n+\n+ if (hdm_id < 0 || hdm_id >= CXL_DC_MAX_DIRECT_MR) {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"Invalid direct window index %d\\n\", hdm_id);\n+ return;\n+ }\n+\n+ if (dcd->dc.total_capacity_cmd > 0) {\n+ mr = &dcd->dc.dc_direct_mr[hdm_id];\n+ } else {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"No dynamic capacity command support, \"\n+ \"cannot remove memory region alias\\n\");\n+ return;\n+ }\n+\n+ if (!fw) {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"Cannot remove memory region alias \"\n+ \"without a valid fixed window\\n\");\n+ return;\n+ }\n+\n+ memory_region_del_subregion(&fw->mr, mr);\n+ dcd->dc.direct_mr_bitmap &= ~(1u << hdm_id);\n+}\n+\n static void ct3_class_init(ObjectClass *oc, const void *data)\n {\n DeviceClass *dc = DEVICE_CLASS(oc);\ndiff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h\nindex 1e904d7b48..42db9c7ce4 100644\n--- a/include/hw/cxl/cxl_device.h\n+++ b/include/hw/cxl/cxl_device.h\n@@ -654,6 +654,7 @@ typedef struct CXLDCExtent {\n uint8_t rsvd[0x6];\n int rid;\n uint64_t offset;\n+ int direct_window_idx;\n \n QTAILQ_ENTRY(CXLDCExtent) node;\n } CXLDCExtent;\n@@ -879,7 +880,8 @@ void cxl_insert_extent_to_extent_list(CXLDCExtentList *list,\n uint8_t *tag,\n uint16_t shared_seq,\n int rid,\n- uint64_t offset);\n+ uint64_t offset,\n+ int direct_window_idx);\n bool test_any_bits_set(const unsigned long *addr, unsigned long nr,\n unsigned long size);\n bool cxl_extents_contains_dpa_range(CXLDCExtentList *list,\n@@ -892,7 +894,8 @@ CXLDCExtentGroup *cxl_insert_extent_to_extent_group(CXLDCExtentGroup *group,\n uint8_t *tag,\n uint16_t shared_seq,\n int rid,\n- uint64_t offset);\n+ uint64_t offset,\n+ int direct_window_idx);\n void cxl_extent_group_list_insert_tail(CXLDCExtentGroupList *list,\n CXLDCExtentGroup *group);\n uint32_t cxl_extent_group_list_delete_front(CXLDCExtentGroupList *list);\n@@ -900,6 +903,8 @@ void ct3_set_region_block_backed(CXLType3Dev *ct3d, uint64_t dpa,\n uint64_t len);\n void ct3_clear_region_block_backed(CXLType3Dev *ct3d, uint64_t dpa,\n uint64_t len);\n+void cxl_remove_memory_alias(CXLType3Dev *dcd, struct CXLFixedWindow *fw,\n+ int hdm_id);\n bool ct3_test_region_block_backed(CXLType3Dev *ct3d, uint64_t dpa,\n uint64_t len);\n void cxl_assign_event_header(CXLEventRecordHdr *hdr,\n","prefixes":["7/9"]}