{"id":2216052,"url":"http://patchwork.ozlabs.org/api/patches/2216052/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260325184259.366-7-alireza.sanaee@huawei.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260325184259.366-7-alireza.sanaee@huawei.com>","list_archive_url":null,"date":"2026-03-25T18:42:54","name":"[6/9] hw/cxl: Create direct fixed-window aliases for accepted extents","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"26c8c1aa8d2a8315ad8f94f4b541d77c151b545b","submitter":{"id":90159,"url":"http://patchwork.ozlabs.org/api/people/90159/?format=json","name":"Alireza Sanaee","email":"alireza.sanaee@huawei.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260325184259.366-7-alireza.sanaee@huawei.com/mbox/","series":[{"id":497484,"url":"http://patchwork.ozlabs.org/api/series/497484/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497484","date":"2026-03-25T18:42:48","name":"Application Specific Tagged Memory Support in CXL Type 3 Devices","version":1,"mbox":"http://patchwork.ozlabs.org/series/497484/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2216052/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2216052/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":"legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n 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2.51.0.windows.2","In-Reply-To":"<20260325184259.366-1-alireza.sanaee@huawei.com>","References":"<20260325184259.366-1-alireza.sanaee@huawei.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-Originating-IP":"[10.47.66.203]","X-ClientProxiedBy":"lhrpeml500011.china.huawei.com (7.191.174.215) To\n dubpeml500005.china.huawei.com (7.214.145.207)","Received-SPF":"pass client-ip=185.176.79.56;\n envelope-from=alireza.sanaee@huawei.com; helo=frasgout.his.huawei.com","X-Spam_score_int":"-41","X-Spam_score":"-4.2","X-Spam_bar":"----","X-Spam_report":"(-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Reply-to":"Alireza Sanaee ","From":"Alireza Sanaee via qemu development ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"For devices using dc-regions-total-size, the fallback read/write path still\nroutes through host_dc_as, but accepted extents are backed by individual\nhost memory backends rather than a single preconfigured address space.\nInstall aliases into the owning fixed window so accepted dynamic-capacity\nmemory is reachable through the normal CXL decoder path.\n\nRecord the non-interleaved decoder window discovered during HDM setup,\nreserve per-device alias slots for lazy DC extents, and create an alias\nfrom the accepted backend into that window when Add Dynamic Capacity\nResponse commits the extent.\n\nThis is scoped to the current non-interleaved direct-mapping model and uses\na small fixed pool of alias slots for now.\n\nSigned-off-by: Alireza Sanaee \n---\n hw/cxl/cxl-host.c | 6 ++++\n hw/cxl/cxl-mailbox-utils.c | 61 +++++++++++++++++++++++++++++--------\n hw/mem/cxl_type3.c | 6 ++--\n include/hw/cxl/cxl_device.h | 18 +++++++++--\n 4 files changed, 75 insertions(+), 16 deletions(-)","diff":"diff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c\nindex 079b27133b..4647754cc9 100644\n--- a/hw/cxl/cxl-host.c\n+++ b/hw/cxl/cxl-host.c\n@@ -300,6 +300,7 @@ static void cxl_fmws_direct_passthrough_setup(CXLDirectPTState *state,\n offset = state->dpa_base - vmr_size;\n }\n }\n+\n if (!mr) {\n return;\n }\n@@ -358,10 +359,15 @@ static int cxl_fmws_direct_passthrough(Object *obj, void *opaque)\n \n /* Verify not interleaved */\n if (!cxl_cfmws_find_device(fw, state->decoder_base, false)) {\n+ state->ct3d->direct_mr_enabled = false;\n return 0;\n }\n+ state->ct3d->direct_mr_enabled = true;\n \n cxl_fmws_direct_passthrough_setup(state, fw);\n+ state->ct3d->dc.fw = fw;\n+ state->ct3d->dc.dc_decoder_window.base = state->decoder_base;\n+ state->ct3d->dc.dc_decoder_window.size = state->decoder_size;\n \n return 0;\n }\ndiff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c\nindex cc7be6e68c..4684c33ba1 100644\n--- a/hw/cxl/cxl-mailbox-utils.c\n+++ b/hw/cxl/cxl-mailbox-utils.c\n@@ -3531,7 +3531,8 @@ void cxl_insert_extent_to_extent_list(CXLDCExtentList *list,\n uint64_t len,\n uint8_t *tag,\n uint16_t shared_seq,\n- int rid)\n+ int rid,\n+ uint64_t offset)\n {\n CXLDCExtent *extent;\n \n@@ -3540,6 +3541,7 @@ void cxl_insert_extent_to_extent_list(CXLDCExtentList *list,\n extent->fw = fw;\n extent->start_dpa = dpa;\n extent->len = len;\n+ extent->offset = offset;\n if (tag) {\n memcpy(extent->tag, tag, 0x10);\n }\n@@ -3568,7 +3570,8 @@ CXLDCExtentGroup *cxl_insert_extent_to_extent_group(CXLDCExtentGroup *group,\n uint64_t len,\n uint8_t *tag,\n uint16_t shared_seq,\n- int rid)\n+ int rid,\n+ uint64_t offset)\n {\n if (!group) {\n group = g_new0(CXLDCExtentGroup, 1);\n@@ -3576,7 +3579,7 @@ CXLDCExtentGroup *cxl_insert_extent_to_extent_group(CXLDCExtentGroup *group,\n }\n cxl_insert_extent_to_extent_list(&group->list,\n host_mem, fw, dpa, len,\n- tag, shared_seq, rid);\n+ tag, shared_seq, rid, offset);\n return group;\n }\n \n@@ -3672,7 +3675,8 @@ static CXLRetCode cxl_detect_malformed_extent_list(CXLType3Dev *ct3d,\n static bool cxl_extent_find_extent_detail(CXLDCExtentGroupList *list,\n uint64_t start_dpa, uint64_t len,\n uint8_t *tag, HostMemoryBackend **hmb,\n- struct CXLFixedWindow **fw, int *rid)\n+ struct CXLFixedWindow **fw, int *rid,\n+ uint64_t *offset)\n {\n CXLDCExtent *ent;\n CXLDCExtentGroup *group = QTAILQ_FIRST(list);\n@@ -3683,6 +3687,7 @@ static bool cxl_extent_find_extent_detail(CXLDCExtentGroupList *list,\n *hmb = ent->hm;\n memcpy(tag, ent->tag, 0x10);\n *rid = ent->rid;\n+ *offset = ent->offset;\n return true;\n }\n }\n@@ -3744,7 +3749,7 @@ static CXLRetCode cmd_dcd_add_dyn_cap_rsp(const struct cxl_cmd *cmd,\n HostMemoryBackend *hmb_dc;\n uint8_t tag[0x10];\n uint32_t i, num;\n- uint64_t dpa, len;\n+ uint64_t dpa, len, offset;\n int rid;\n CXLRetCode ret;\n \n@@ -3783,12 +3788,14 @@ static CXLRetCode cmd_dcd_add_dyn_cap_rsp(const struct cxl_cmd *cmd,\n dpa = in->updated_entries[i].start_dpa;\n len = in->updated_entries[i].len;\n if (ct3d->dc.total_capacity_cmd) {\n+ int mr_idx = -1;\n bool found;\n MemoryRegion *mr;\n \n found = cxl_extent_find_extent_detail(&ct3d->dc.extents_pending,\n dpa, len, tag,\n- &hmb_dc, &fw, &rid);\n+ &hmb_dc, &fw, &rid,\n+ &offset);\n \n /*\n * Host accepted an extent where device lacks details including\n@@ -3822,13 +3829,38 @@ static CXLRetCode cmd_dcd_add_dyn_cap_rsp(const struct cxl_cmd *cmd,\n memory_region_set_enabled(mr, true);\n host_memory_backend_set_mapped(hmb_dc, true);\n \n+ /* Optional direct alias mapping into fixed memory window */\n+ if (ct3d->direct_mr_enabled) {\n+ uint32_t full_mask = (1u << CXL_DC_MAX_DIRECT_MR) - 1;\n+ if ((ct3d->dc.direct_mr_bitmap & full_mask) == full_mask) {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"Out of direct mapping slots\\n\");\n+ return CXL_MBOX_RESOURCES_EXHAUSTED;\n+ }\n+ mr_idx = ctz32(~ct3d->dc.direct_mr_bitmap);\n+ g_autofree char *direct_mapping_name =\n+ g_strdup_printf(\"cxl-direct-mapping-%d\", mr_idx);\n+ hwaddr region_offset = dpa - ct3d->dc.regions[rid].base;\n+ MemoryRegion *dr_dc_mr = &ct3d->dc.dc_direct_mr[mr_idx];\n+\n+ memory_region_init_alias(dr_dc_mr, OBJECT(ct3d),\n+ direct_mapping_name, mr,\n+ region_offset,\n+ ct3d->dc.dc_decoder_window.size);\n+ memory_region_add_subregion(&fw->mr,\n+ ct3d->dc.dc_decoder_window.base - fw->base + offset,\n+ dr_dc_mr);\n+\n+ ct3d->dc.direct_mr_bitmap |= (1u << mr_idx);\n+ }\n+\n cxl_insert_extent_to_extent_list(extent_list,\n hmb_dc, fw, dpa, len,\n- NULL, 0, rid);\n+ tag, 0, rid, offset);\n } else {\n cxl_insert_extent_to_extent_list(extent_list,\n NULL, NULL, dpa, len,\n- NULL, 0, -1);\n+ NULL, 0, -1, (uint64_t)-1);\n }\n ct3d->dc.total_extent_count += 1;\n ct3d->dc.nr_extents_accepted += 1;\n@@ -3860,7 +3892,7 @@ static uint32_t copy_extent_list(CXLDCExtentList *dst,\n ent->hm, ent->fw,\n ent->start_dpa, ent->len,\n ent->tag, ent->shared_seq,\n- ent->rid);\n+ ent->rid, ent->offset);\n cnt++;\n }\n return cnt;\n@@ -3917,14 +3949,18 @@ static CXLRetCode cxl_dc_extent_release_dry_run(CXLType3Dev *ct3d,\n cxl_insert_extent_to_extent_list(updated_list,\n NULL, NULL,\n ent_start_dpa, len1,\n- NULL, 0, ent->rid);\n+ ent->tag, 0,\n+ ent->rid,\n+ ent->offset);\n cnt_delta++;\n }\n if (len2) {\n cxl_insert_extent_to_extent_list(updated_list,\n NULL, NULL,\n dpa + len, len2,\n- NULL, 0, ent->rid);\n+ ent->tag, 0,\n+ ent->rid,\n+ ent->offset);\n cnt_delta++;\n }\n \n@@ -4401,7 +4437,8 @@ static CXLRetCode cmd_fm_initiate_dc_add(const struct cxl_cmd *cmd,\n NULL, NULL,\n ext->start_dpa,\n ext->len, ext->tag,\n- ext->shared_seq, 0);\n+ ext->shared_seq, 0,\n+ (uint64_t)-1);\n }\n \n cxl_extent_group_list_insert_tail(&ct3d->dc.extents_pending, group);\ndiff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c\nindex bd32532c7a..e13826eb0b 100644\n--- a/hw/mem/cxl_type3.c\n+++ b/hw/mem/cxl_type3.c\n@@ -2464,7 +2464,8 @@ static void qmp_cxl_process_dynamic_capacity_prescriptive(const char *path,\n extents[i].len,\n extents[i].tag,\n extents[i].shared_seq,\n- rid);\n+ rid,\n+ offset);\n } else {\n group = cxl_insert_extent_to_extent_group(group,\n dcd->dc.host_dc,\n@@ -2473,7 +2474,8 @@ static void qmp_cxl_process_dynamic_capacity_prescriptive(const char *path,\n extents[i].len,\n extents[i].tag,\n extents[i].shared_seq,\n- rid);\n+ rid,\n+ offset);\n }\n }\n \ndiff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h\nindex a84b8ab358..1e904d7b48 100644\n--- a/include/hw/cxl/cxl_device.h\n+++ b/include/hw/cxl/cxl_device.h\n@@ -634,6 +634,7 @@ typedef struct CXLMemSparingWriteAttrs {\n #define CXL_MEMDEV_SOFT_SPARING_SUPPORT_FLAG BIT(2)\n \n #define DCD_MAX_NUM_REGION 8\n+#define CXL_DC_MAX_DIRECT_MR 4\n \n typedef struct CXLDCExtentRaw {\n uint64_t start_dpa;\n@@ -652,6 +653,7 @@ typedef struct CXLDCExtent {\n uint16_t shared_seq;\n uint8_t rsvd[0x6];\n int rid;\n+ uint64_t offset;\n \n QTAILQ_ENTRY(CXLDCExtent) node;\n } CXLDCExtent;\n@@ -720,6 +722,7 @@ struct CXLType3Dev {\n /* State */\n MemoryRegion direct_mr[CXL_HDM_DECODER_COUNT];\n CXLFixedWindow *direct_mr_fw[CXL_HDM_DECODER_COUNT];\n+ bool direct_mr_enabled;\n AddressSpace hostvmem_as;\n AddressSpace hostpmem_as;\n CXLComponentState cxl_cstate;\n@@ -785,6 +788,14 @@ struct CXLType3Dev {\n HostMemoryBackend *host_dc;\n AddressSpace host_dc_as;\n struct CXLFixedWindow *fw;\n+ uint32_t direct_mr_bitmap;\n+ /*\n+ * dc_decoder_window represents the CXL Decoder Window\n+ */\n+ struct decoder_window {\n+ hwaddr base;\n+ hwaddr size;\n+ } dc_decoder_window;\n /*\n * total_capacity is equivalent to the dynamic capability\n * memory region size.\n@@ -799,6 +810,7 @@ struct CXLType3Dev {\n \n uint8_t num_regions; /* 0-8 regions */\n CXLDCRegion regions[DCD_MAX_NUM_REGION];\n+ MemoryRegion dc_direct_mr[CXL_DC_MAX_DIRECT_MR];\n } dc;\n \n struct CXLSanitizeInfo *media_op_sanitize;\n@@ -866,7 +878,8 @@ void cxl_insert_extent_to_extent_list(CXLDCExtentList *list,\n uint64_t len,\n uint8_t *tag,\n uint16_t shared_seq,\n- int rid);\n+ int rid,\n+ uint64_t offset);\n bool test_any_bits_set(const unsigned long *addr, unsigned long nr,\n unsigned long size);\n bool cxl_extents_contains_dpa_range(CXLDCExtentList *list,\n@@ -878,7 +891,8 @@ CXLDCExtentGroup *cxl_insert_extent_to_extent_group(CXLDCExtentGroup *group,\n uint64_t len,\n uint8_t *tag,\n uint16_t shared_seq,\n- int rid);\n+ int rid,\n+ uint64_t offset);\n void cxl_extent_group_list_insert_tail(CXLDCExtentGroupList *list,\n CXLDCExtentGroup *group);\n uint32_t cxl_extent_group_list_delete_front(CXLDCExtentGroupList *list);\n","prefixes":["6/9"]}