{"id":2215830,"url":"http://patchwork.ozlabs.org/api/patches/2215830/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260325120944.29391-3-thuth@redhat.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260325120944.29391-3-thuth@redhat.com>","list_archive_url":null,"date":"2026-03-25T12:09:44","name":"[2/2] target/i386/tcg/sysemu: Allow 32-bit SMM code to be used in the 64-bit binary","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"93fa5f95b14d3b229c7ebb9c13abb2da27bdfb8c","submitter":{"id":66152,"url":"http://patchwork.ozlabs.org/api/people/66152/?format=json","name":"Thomas Huth","email":"thuth@redhat.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260325120944.29391-3-thuth@redhat.com/mbox/","series":[{"id":497430,"url":"http://patchwork.ozlabs.org/api/series/497430/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497430","date":"2026-03-25T12:09:42","name":"target/i386: Allow 32-bit SMM code to be used in the 64-bit binary","version":1,"mbox":"http://patchwork.ozlabs.org/series/497430/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2215830/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2215830/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256\n header.s=mimecast20190719 header.b=VxvKfpVH;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com;\n s=mimecast20190719; t=1774440596;\n h=from:from:reply-to:subject:subject:date:date:message-id:message-id:\n to:to:cc:cc:mime-version:mime-version:\n content-transfer-encoding:content-transfer-encoding:\n in-reply-to:in-reply-to:references:references;\n bh=SdGyZXxwTYuvuSTrhC9NuPS6j2R9Ll8NKs9BQm1mdDs=;\n b=VxvKfpVHCuXcLigkEhN4uuFb71ipC0ENmwXNPTuD5itQ0C7j6Rfqd4nH2dycpfOWR9LQg0\n S7E4vrCXRwjmvsV8DkVEOw/UrjXK3cIRPPfgnrkkGca+E9FK1hUsauztCbnOyb6VKIQ5wb\n JxF6heasfhfacdcyWDeSawhxb8ssUJY=","X-MC-Unique":"ZODADJreNj2j6q6vA7L1Aw-1","X-Mimecast-MFC-AGG-ID":"ZODADJreNj2j6q6vA7L1Aw_1774440593","From":"Thomas Huth ","To":"Paolo Bonzini ,\n\tqemu-devel@nongnu.org","Cc":"Richard Henderson , =?utf-8?q?Philippe_Mat?=\n\t=?utf-8?q?hieu-Daud=C3=A9?= ,\n Pierrick Bouvier ","Subject":"[PATCH 2/2] target/i386/tcg/sysemu: Allow 32-bit SMM code to be used\n in the 64-bit binary","Date":"Wed, 25 Mar 2026 13:09:44 +0100","Message-ID":"<20260325120944.29391-3-thuth@redhat.com>","In-Reply-To":"<20260325120944.29391-1-thuth@redhat.com>","References":"<20260325120944.29391-1-thuth@redhat.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Scanned-By":"MIMEDefang 3.0 on 10.30.177.12","Received-SPF":"pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com;\n helo=us-smtp-delivery-124.mimecast.com","X-Spam_score_int":"12","X-Spam_score":"1.2","X-Spam_bar":"+","X-Spam_report":"(1.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001,\n RCVD_IN_SBL_CSS=3.335, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Thomas Huth \n\nThis is a preparation for the QEMU universal binary where we might want\nto support both, the x86_64 and the i386 target, in one binary. Instead\nof using #ifdef TARGET_X86_64 here, check the LM bit to select the 32-bit\nor 64-bit code during runtime.\n\nSigned-off-by: Thomas Huth \n---\n target/i386/tcg/system/smm_helper.c | 65 +++++++++++++++++++----------\n 1 file changed, 43 insertions(+), 22 deletions(-)","diff":"diff --git a/target/i386/tcg/system/smm_helper.c b/target/i386/tcg/system/smm_helper.c\nindex 3be78cd53d3..4bbe18a86fb 100644\n--- a/target/i386/tcg/system/smm_helper.c\n+++ b/target/i386/tcg/system/smm_helper.c\n@@ -23,24 +23,15 @@\n #include \"exec/log.h\"\n #include \"tcg/helper-tcg.h\"\n \n-\n-/* SMM support */\n-\n-#ifdef TARGET_X86_64\n-#define SMM_REVISION_ID 0x00020064\n-#else\n-#define SMM_REVISION_ID 0x00020000\n-#endif\n-\n-static void sm_state_init(X86CPU *cpu)\n+static void sm_state_init_64(X86CPU *cpu)\n {\n+#ifdef TARGET_X86_64\n CPUX86State *env = &cpu->env;\n CPUState *cs = CPU(cpu);\n SegmentCache *dt;\n int i, offset;\n target_ulong sm_state = env->smbase + 0x8000;\n \n-#ifdef TARGET_X86_64\n for (i = 0; i < 6; i++) {\n dt = &env->segs[i];\n offset = 0x7e00 + i * 16;\n@@ -92,9 +83,21 @@ static void sm_state_init(X86CPU *cpu)\n x86_stq_phys(cs, sm_state + 0x7f50, env->cr[3]);\n x86_stl_phys(cs, sm_state + 0x7f58, env->cr[0]);\n \n- x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID);\n+ x86_stl_phys(cs, sm_state + 0x7efc, 0x00020064); /* SMM revision ID */\n x86_stl_phys(cs, sm_state + 0x7f00, env->smbase);\n #else\n+ g_assert_not_reached();\n+#endif\n+}\n+\n+static void sm_state_init_32(X86CPU *cpu)\n+{\n+ CPUX86State *env = &cpu->env;\n+ CPUState *cs = CPU(cpu);\n+ SegmentCache *dt;\n+ int i, offset;\n+ target_ulong sm_state = env->smbase + 0x8000;\n+\n x86_stl_phys(cs, sm_state + 0x7ffc, env->cr[0]);\n x86_stl_phys(cs, sm_state + 0x7ff8, env->cr[3]);\n x86_stl_phys(cs, sm_state + 0x7ff4, cpu_compute_eflags(env));\n@@ -140,9 +143,8 @@ static void sm_state_init(X86CPU *cpu)\n }\n x86_stl_phys(cs, sm_state + 0x7f14, env->cr[4]);\n \n- x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID);\n+ x86_stl_phys(cs, sm_state + 0x7efc, 0x00020000); /* SMM revision ID */\n x86_stl_phys(cs, sm_state + 0x7ef8, env->smbase);\n-#endif\n }\n \n void do_smm_enter(X86CPU *cpu)\n@@ -160,13 +162,15 @@ void do_smm_enter(X86CPU *cpu)\n env->hflags2 |= HF2_NMI_MASK;\n }\n \n- sm_state_init(cpu);\n+ if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {\n+ sm_state_init_64(cpu);\n+ cpu_load_efer(env, 0);\n+ } else {\n+ sm_state_init_32(cpu);\n+ }\n \n /* init SMM cpu state */\n \n-#ifdef TARGET_X86_64\n- cpu_load_efer(env, 0);\n-#endif\n cpu_load_eflags(env, 0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C |\n DF_MASK));\n env->eip = 0x00008000;\n@@ -197,15 +201,16 @@ void do_smm_enter(X86CPU *cpu)\n DESC_G_MASK | DESC_A_MASK);\n }\n \n-static void rsm_load_regs(CPUX86State *env)\n+static void rsm_load_regs_64(CPUX86State *env)\n {\n+#ifdef TARGET_X86_64\n CPUState *cs = env_cpu(env);\n target_ulong sm_state;\n int i, offset;\n uint32_t val;\n \n sm_state = env->smbase + 0x8000;\n-#ifdef TARGET_X86_64\n+\n cpu_load_efer(env, x86_ldq_phys(cs, sm_state + 0x7ed0));\n \n env->gdt.base = x86_ldq_phys(cs, sm_state + 0x7e68);\n@@ -260,6 +265,19 @@ static void rsm_load_regs(CPUX86State *env)\n env->smbase = x86_ldl_phys(cs, sm_state + 0x7f00);\n }\n #else\n+ g_assert_not_reached();\n+#endif\n+}\n+\n+static void rsm_load_regs_32(CPUX86State *env)\n+{\n+ CPUState *cs = env_cpu(env);\n+ target_ulong sm_state;\n+ int i, offset;\n+ uint32_t val;\n+\n+ sm_state = env->smbase + 0x8000;\n+\n cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7ffc));\n cpu_x86_update_cr3(env, x86_ldl_phys(cs, sm_state + 0x7ff8));\n cpu_load_eflags(env, x86_ldl_phys(cs, sm_state + 0x7ff4),\n@@ -312,14 +330,17 @@ static void rsm_load_regs(CPUX86State *env)\n if (val & 0x20000) {\n env->smbase = x86_ldl_phys(cs, sm_state + 0x7ef8);\n }\n-#endif\n }\n \n void helper_rsm(CPUX86State *env)\n {\n X86CPU *cpu = env_archcpu(env);\n \n- rsm_load_regs(env);\n+ if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {\n+ rsm_load_regs_64(env);\n+ } else {\n+ rsm_load_regs_32(env);\n+ }\n \n if ((env->hflags2 & HF2_SMM_INSIDE_NMI_MASK) == 0) {\n env->hflags2 &= ~HF2_NMI_MASK;\n","prefixes":["2/2"]}