{"id":2215795,"url":"http://patchwork.ozlabs.org/api/patches/2215795/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pwm/patch/20260325-t264-pwm-v2-3-998d885984b3@nvidia.com/","project":{"id":38,"url":"http://patchwork.ozlabs.org/api/projects/38/?format=json","name":"Linux PWM development","link_name":"linux-pwm","list_id":"linux-pwm.vger.kernel.org","list_email":"linux-pwm@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260325-t264-pwm-v2-3-998d885984b3@nvidia.com>","list_archive_url":null,"date":"2026-03-25T10:17:01","name":"[v2,3/7] pwm: tegra: Modify read/write accessors for multi-register channel","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"f23f6ba356c950af779d63966c05db4b1be2106d","submitter":{"id":26499,"url":"http://patchwork.ozlabs.org/api/people/26499/?format=json","name":"Mikko Perttunen","email":"mperttunen@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pwm/patch/20260325-t264-pwm-v2-3-998d885984b3@nvidia.com/mbox/","series":[{"id":497412,"url":"http://patchwork.ozlabs.org/api/series/497412/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pwm/list/?series=497412","date":"2026-03-25T10:17:00","name":"Tegra264 PWM support","version":2,"mbox":"http://patchwork.ozlabs.org/series/497412/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2215795/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2215795/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pwm@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260325-t264-pwm-v2-3-998d885984b3@nvidia.com>","References":"<20260325-t264-pwm-v2-0-998d885984b3@nvidia.com>","In-Reply-To":"<20260325-t264-pwm-v2-0-998d885984b3@nvidia.com>","To":"Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6n?=\n\t=?utf-8?q?ig?= ,\n Jonathan Hunter , Rob Herring ,\n Krzysztof Kozlowski ,\n Conor Dooley ","Cc":"linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org,\n linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,\n Mikko Perttunen ","X-Mailer":"b4 0.14.3","X-ClientProxiedBy":"TPYP295CA0057.TWNP295.PROD.OUTLOOK.COM (2603:1096:7d0:8::8)\n To SJ2PR12MB9161.namprd12.prod.outlook.com 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ed7d31c6-8bbc-41e4-9dcc-08de8a57c579","X-MS-Exchange-CrossTenant-AuthSource":"SJ2PR12MB9161.namprd12.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"25 Mar 2026 10:17:51.5168\n (UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"43083d15-7273-40c1-b7db-39efd9ccc17a","X-MS-Exchange-CrossTenant-MailboxType":"HOSTED","X-MS-Exchange-CrossTenant-UserPrincipalName":"\n pGXs1R1ueaNDk4y7k3NxEjQzQHXrqg9k4eajKG/MOo83SDoHJzAaOnzU5uTfyRLyy8Y23h+xi8eBid16cwoPzw==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"DS5PPFA3734E4BA"},"content":"On Tegra264, each PWM instance has two registers (per channel, of which\nthere is one). Update the pwm_readl/pwm_writel helper functions to\ntake channel (as struct pwm_device *) and offset separately.\n\nSigned-off-by: Mikko Perttunen \n---\n drivers/pwm/pwm-tegra.c | 26 +++++++++++++++-----------\n 1 file changed, 15 insertions(+), 11 deletions(-)","diff":"diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c\nindex 759b98b97b6e..cf54f75d92a5 100644\n--- a/drivers/pwm/pwm-tegra.c\n+++ b/drivers/pwm/pwm-tegra.c\n@@ -57,6 +57,8 @@\n #define PWM_SCALE_WIDTH\t13\n #define PWM_SCALE_SHIFT\t0\n \n+#define PWM_CSR_0\t0\n+\n struct tegra_pwm_soc {\n \tunsigned int num_channels;\n };\n@@ -78,14 +80,18 @@ static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip)\n \treturn pwmchip_get_drvdata(chip);\n }\n \n-static inline u32 pwm_readl(struct tegra_pwm_chip *pc, unsigned int offset)\n+static inline u32 pwm_readl(struct pwm_device *dev, unsigned int offset)\n {\n-\treturn readl(pc->regs + (offset << 4));\n+\tstruct tegra_pwm_chip *chip = to_tegra_pwm_chip(dev->chip);\n+\n+\treturn readl(chip->regs + (dev->hwpwm * 16) + offset);\n }\n \n-static inline void pwm_writel(struct tegra_pwm_chip *pc, unsigned int offset, u32 value)\n+static inline void pwm_writel(struct pwm_device *dev, unsigned int offset, u32 value)\n {\n-\twritel(value, pc->regs + (offset << 4));\n+\tstruct tegra_pwm_chip *chip = to_tegra_pwm_chip(dev->chip);\n+\n+\twritel(value, chip->regs + (dev->hwpwm * 16) + offset);\n }\n \n static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,\n@@ -194,7 +200,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,\n \t} else\n \t\tval |= PWM_ENABLE;\n \n-\tpwm_writel(pc, pwm->hwpwm, val);\n+\tpwm_writel(pwm, PWM_CSR_0, val);\n \n \t/*\n \t * If the PWM is not enabled, turn the clock off again to save power.\n@@ -207,7 +213,6 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,\n \n static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)\n {\n-\tstruct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);\n \tint rc = 0;\n \tu32 val;\n \n@@ -215,21 +220,20 @@ static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)\n \tif (rc)\n \t\treturn rc;\n \n-\tval = pwm_readl(pc, pwm->hwpwm);\n+\tval = pwm_readl(pwm, PWM_CSR_0);\n \tval |= PWM_ENABLE;\n-\tpwm_writel(pc, pwm->hwpwm, val);\n+\tpwm_writel(pwm, PWM_CSR_0, val);\n \n \treturn 0;\n }\n \n static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)\n {\n-\tstruct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);\n \tu32 val;\n \n-\tval = pwm_readl(pc, pwm->hwpwm);\n+\tval = pwm_readl(pwm, PWM_CSR_0);\n \tval &= ~PWM_ENABLE;\n-\tpwm_writel(pc, pwm->hwpwm, val);\n+\tpwm_writel(pwm, PWM_CSR_0, val);\n \n \tpm_runtime_put_sync(pwmchip_parent(chip));\n }\n","prefixes":["v2","3/7"]}