{"id":2215789,"url":"http://patchwork.ozlabs.org/api/patches/2215789/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pwm/patch/20260325-t264-pwm-v2-6-998d885984b3@nvidia.com/","project":{"id":38,"url":"http://patchwork.ozlabs.org/api/projects/38/?format=json","name":"Linux PWM development","link_name":"linux-pwm","list_id":"linux-pwm.vger.kernel.org","list_email":"linux-pwm@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260325-t264-pwm-v2-6-998d885984b3@nvidia.com>","list_archive_url":null,"date":"2026-03-25T10:17:04","name":"[v2,6/7] pwm: tegra: Add support for Tegra264","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"2b4b091067139932ae074d98953a4b7862163ae7","submitter":{"id":26499,"url":"http://patchwork.ozlabs.org/api/people/26499/?format=json","name":"Mikko Perttunen","email":"mperttunen@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pwm/patch/20260325-t264-pwm-v2-6-998d885984b3@nvidia.com/mbox/","series":[{"id":497412,"url":"http://patchwork.ozlabs.org/api/series/497412/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pwm/list/?series=497412","date":"2026-03-25T10:17:00","name":"Tegra264 PWM support","version":2,"mbox":"http://patchwork.ozlabs.org/series/497412/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2215789/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2215789/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pwm@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 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d2f1a4c2-6f10-4d36-c3d9-08de8a57cd6a","X-MS-Exchange-CrossTenant-AuthSource":"SJ2PR12MB9161.namprd12.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"25 Mar 2026 10:18:04.8425\n (UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"43083d15-7273-40c1-b7db-39efd9ccc17a","X-MS-Exchange-CrossTenant-MailboxType":"HOSTED","X-MS-Exchange-CrossTenant-UserPrincipalName":"\n wuRxXa5IhzMO9EkRlx4UjFwleAgtbhTuLiAAJVhAnTq62qvl+JVXXFz8pon3Ns5fvI3nqs2TVUUrmFWmgPFK+A==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"DS5PPFA3734E4BA"},"content":"Tegra264 changes the register layout to accommodate wider fields\nfor duty and scale, and adds configurable depth which will be\nsupported in a later patch.\n\nAdd SoC data and update top comment to describe register layout\nin more detail.\n\nCo-developed-by: Yi-Wei Wang \nSigned-off-by: Yi-Wei Wang \nSigned-off-by: Mikko Perttunen \n---\n drivers/pwm/pwm-tegra.c | 75 ++++++++++++++++++++++++++++++++++++++++---------\n 1 file changed, 61 insertions(+), 14 deletions(-)","diff":"diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c\nindex 857301baad51..c1e8a804d783 100644\n--- a/drivers/pwm/pwm-tegra.c\n+++ b/drivers/pwm/pwm-tegra.c\n@@ -7,22 +7,60 @@\n * Copyright (c) 2010-2020, NVIDIA Corporation.\n * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer \n *\n- * Overview of Tegra Pulse Width Modulator Register:\n- * 1. 13-bit: Frequency division (SCALE)\n- * 2. 8-bit : Pulse division (DUTY)\n- * 3. 1-bit : Enable bit\n+ * Overview of Tegra Pulse Width Modulator Register\n+ * CSR_0 of Tegra20, Tegra186, and Tegra194:\n+ * +-------+-------+-----------------------------------------------------------+\n+ * | Bit | Field | Description |\n+ * +-------+-------+-----------------------------------------------------------+\n+ * | 31 | ENB | Enable Pulse width modulator. |\n+ * | | | 0 = DISABLE, 1 = ENABLE. |\n+ * +-------+-------+-----------------------------------------------------------+\n+ * | 30:16 | PWM_0 | Pulse width that needs to be programmed. |\n+ * | | | 0 = Always low. |\n+ * | | | 1 = 1 / 256 pulse high. |\n+ * | | | 2 = 2 / 256 pulse high. |\n+ * | | | N = N / 256 pulse high. |\n+ * | | | Only 8 bits are usable [23:16]. |\n+ * | | | Bit[24] can be programmed to 1 to achieve 100% duty |\n+ * | | | cycle. In this case the other bits [23:16] are set to |\n+ * | | | don’t care. |\n+ * +-------+-------+-----------------------------------------------------------+\n+ * | 12:0 | PFM_0 | Frequency divider that needs to be programmed, also known |\n+ * | | | as SCALE. Division by (1 + PFM_0). |\n+ * +-------+-------+-----------------------------------------------------------+\n *\n- * The PWM clock frequency is divided by 256 before subdividing it based\n- * on the programmable frequency division value to generate the required\n- * frequency for PWM output. The maximum output frequency that can be\n- * achieved is (max rate of source clock) / 256.\n- * e.g. if source clock rate is 408 MHz, maximum output frequency can be:\n- * 408 MHz/256 = 1.6 MHz.\n- * This 1.6 MHz frequency can further be divided using SCALE value in PWM.\n+ * CSR_0 of Tegra264:\n+ * +-------+-------+-----------------------------------------------------------+\n+ * | Bit | Field | Description |\n+ * +-------+-------+-----------------------------------------------------------+\n+ * | 31:16 | PWM_0 | Pulse width that needs to be programmed. |\n+ * | | | 0 = Always low. |\n+ * | | | 1 = 1 / (1 + CSR_1.DEPTH) pulse high. |\n+ * | | | 2 = 2 / (1 + CSR_1.DEPTH) pulse high. |\n+ * | | | N = N / (1 + CSR_1.DEPTH) pulse high. |\n+ * +-------+-------+-----------------------------------------------------------+\n+ * | 15:0 | PFM_0 | Frequency divider that needs to be programmed, also known |\n+ * | | | as SCALE. Division by (1 + PFM_0). |\n+ * +-------+-------+-----------------------------------------------------------+\n+ *\n+ * CSR_1 of Tegra264:\n+ * +-------+-------+-----------------------------------------------------------+\n+ * | Bit | Field | Description |\n+ * +-------+-------+-----------------------------------------------------------+\n+ * | 31 | ENB | Enable Pulse width modulator. |\n+ * | | | 0 = DISABLE, 1 = ENABLE. |\n+ * +-------+-------+-----------------------------------------------------------+\n+ * | 30:15 | DEPTH | Depth for pulse width modulator. This controls the pulse |\n+ * | | | time generated. Division by (1 + CSR_1.DEPTH). |\n+ * +-------+-------+-----------------------------------------------------------+\n *\n- * PWM pulse width: 8 bits are usable [23:16] for varying pulse width.\n- * To achieve 100% duty cycle, program Bit [24] of this register to\n- * 1’b1. In which case the other bits [23:16] are set to don't care.\n+ * The PWM clock frequency is divided by DEPTH = (1 + CSR_1.DEPTH) before subdividing it\n+ * based on the programmable frequency division value to generate the required frequency\n+ * for PWM output. DEPTH is fixed to 256 before Tegra264. The maximum output frequency\n+ * that can be achieved is (max rate of source clock) / DEPTH.\n+ * e.g. if source clock rate is 408 MHz, and DEPTH = 256, maximum output frequency can be:\n+ * 408 MHz / 256 ~= 1.6 MHz.\n+ * This 1.6 MHz frequency can further be divided using SCALE value in PWM.\n *\n * Limitations:\n * -\tWhen PWM is disabled, the output is driven to inactive.\n@@ -56,6 +94,7 @@\n #define PWM_SCALE_SHIFT\t0\n \n #define PWM_CSR_0\t0\n+#define PWM_CSR_1\t4\n \n #define PWM_DEPTH\t256\n \n@@ -418,10 +457,18 @@ static const struct tegra_pwm_soc tegra186_pwm_soc = {\n \t.scale_width = 13,\n };\n \n+static const struct tegra_pwm_soc tegra264_pwm_soc = {\n+\t.num_channels = 1,\n+\t.enable_reg = PWM_CSR_1,\n+\t.duty_width = 16,\n+\t.scale_width = 16,\n+};\n+\n static const struct of_device_id tegra_pwm_of_match[] = {\n \t{ .compatible = \"nvidia,tegra20-pwm\", .data = &tegra20_pwm_soc },\n \t{ .compatible = \"nvidia,tegra186-pwm\", .data = &tegra186_pwm_soc },\n \t{ .compatible = \"nvidia,tegra194-pwm\", .data = &tegra186_pwm_soc },\n+\t{ .compatible = \"nvidia,tegra264-pwm\", .data = &tegra264_pwm_soc },\n \t{ }\n };\n MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);\n","prefixes":["v2","6/7"]}