{"id":2215779,"url":"http://patchwork.ozlabs.org/api/patches/2215779/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260325101437.3059693-10-sheetal@nvidia.com/","project":{"id":21,"url":"http://patchwork.ozlabs.org/api/projects/21/?format=json","name":"Linux Tegra Development","link_name":"linux-tegra","list_id":"linux-tegra.vger.kernel.org","list_email":"linux-tegra@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260325101437.3059693-10-sheetal@nvidia.com>","list_archive_url":null,"date":"2026-03-25T10:14:32","name":"[v3,09/14] ASoC: tegra: Use dev_err_probe() in OPE, PEQ and MBDRC drivers","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"6ab627b87e4b738685c96624039d7ecb29f8238b","submitter":{"id":87986,"url":"http://patchwork.ozlabs.org/api/people/87986/?format=json","name":"Sheetal","email":"sheetal@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260325101437.3059693-10-sheetal@nvidia.com/mbox/","series":[{"id":497410,"url":"http://patchwork.ozlabs.org/api/series/497410/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/list/?series=497410","date":"2026-03-25T10:14:23","name":"ASoC: tegra: Add error logging for probe and callback failures","version":3,"mbox":"http://patchwork.ozlabs.org/series/497410/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2215779/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2215779/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=DKAhz2jF;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-tegra+bounces-13188-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=\"DKAhz2jF\"","smtp.subspace.kernel.org;\n arc=fail smtp.client-ip=52.101.62.40","smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com","smtp.subspace.kernel.org;\n spf=fail smtp.mailfrom=nvidia.com"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fgjdd6yxbz1xy1\n\tfor ; Wed, 25 Mar 2026 21:22:29 +1100 (AEDT)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id DC9BA304BCC9\n\tfor ; Wed, 25 Mar 2026 10:15:44 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id B99B13A543E;\n\tWed, 25 Mar 2026 10:15:44 +0000 (UTC)","from DM5PR21CU001.outbound.protection.outlook.com\n (mail-centralusazon11011040.outbound.protection.outlook.com [52.101.62.40])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 833E139DBC0;\n\tWed, 25 Mar 2026 10:15:42 +0000 (UTC)","from MN2PR06CA0017.namprd06.prod.outlook.com (2603:10b6:208:23d::22)\n by CH1PPFC908D89D1.namprd12.prod.outlook.com (2603:10b6:61f:fc00::623) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9745.9; Wed, 25 Mar\n 2026 10:15:37 +0000","from BL02EPF00021F6E.namprd02.prod.outlook.com\n (2603:10b6:208:23d:cafe::a) by MN2PR06CA0017.outlook.office365.com\n (2603:10b6:208:23d::22) with Microsoft SMTP Server (version=TLS1_3,\n cipher=TLS_AES_256_GCM_SHA384) id 15.20.9723.32 via Frontend Transport; Wed,\n 25 Mar 2026 10:15:15 +0000","from mail.nvidia.com (216.228.118.233) by\n BL02EPF00021F6E.mail.protection.outlook.com (10.167.249.10) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.9745.21 via Frontend Transport; Wed, 25 Mar 2026 10:15:37 +0000","from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com\n (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 25 Mar\n 2026 03:15:24 -0700","from drhqmail202.nvidia.com (10.126.190.181) by\n drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.2562.20; Wed, 25 Mar 2026 03:15:24 -0700","from build-sheetal-bionic-20251202.nvidia.com (10.127.8.14) by\n mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.2562.20\n via Frontend Transport; Wed, 25 Mar 2026 03:15:23 -0700"],"ARC-Seal":["i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1774433744; cv=fail;\n b=UG0U7AZs0InSQtZ+sO/6DameNhih0fb7VjwvTuOwEMWOI/g/fVP5pH5aZGy2QIhaugd6wiuV+1Ap+2/WfeTl0rTgOayJhFh5IKdnvzPD8uR1F1tGxX1WL/XftjP6JxxYoy4sxDj5xYgnMdFjwF6upAcvZDYTPZ30Q8+FAiwpW4Y=","i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=kZSWP0YHOkVi0z9Gcy3tIPWQ9ikMZerY5vGgMJRJHZFMhaOUTKUSfNZnaYaZKj9REjlh+H7AHP34UX6/vvH70VqibCxs/ES3kvTgeJFp3Te7DpeJeukEkdUn4vpcnBN6VM6/9GvxzreCq2stXWeLRm7sb+NyK0sjfCSay3QkIZKu7uswGTjqVal9bdb1NCCCBVteHH+axltMol9/jmY8k+qOtyKdd9BF3SiZf7GKxE4JbmOfGzgnE5TFG8NNaCH10rcim1i2X2Oj80Xy/iLriEFdy76IINy6uNSH1IhU7PEJfbUisHralS4q+yHZnZvyUJDXWVD9Jegzd8iArYRsrw=="],"ARC-Message-Signature":["i=2; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1774433744; c=relaxed/simple;\n\tbh=G7AhijhD0q6OOWRO5gWIUDGBTw9NEBjvY9auk6dudSY=;\n\th=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version:Content-Type;\n b=Ew1AcWoVniShwe6CPcqIbMZs1fqCimwtXuqIHjMLAL++QmJU1ewQ6yO9BGziI6AAB0SPYtgs9fxyIfa4Vz7CiXVAOvfOqDNnWttXeq+5rLJZgNx7cc5SA/OICSBEIN0kv0Efqxn2qfbzsRGRv4H9xHf409F/IKgkwUgZvLb0A+4=","i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=kMnGmS0HCMjRP2HhtDMiezX11p9ZCg3sxc+q8fGzVIE=;\n b=VPZaK0siraUNfsbzhu+TNAyH50IhLgXUzEH6ox/ym3w0FfO49AxhjtbtcM83+kBHQOQeYr58xi17com3aB/mf+K8xfd4apMC6E17c/HkdTX+qJRb9WXtn6UrEX7OIokxstXboeD/HXGoQt8nVwOc1BPpeALxfV22a7WzAzDeEwrvxvqCoxPG57orCQ/wS5wRByAQcZALLLDn2pIVpl7gZNfoer7o+pK6qZ64ZxXfzXPEWJG9tHc6jGXrXKQX83djSwPPziiz2ibyDmakWP5eujzwksERhkzOBX8VYAZYT13eCHs3qnd8CqLcqX4CGUGJ9CxpeycJiOrd9lqlr7xOlw=="],"ARC-Authentication-Results":["i=2; smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com;\n spf=fail smtp.mailfrom=nvidia.com;\n dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=DKAhz2jF; arc=fail smtp.client-ip=52.101.62.40","i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.118.233) smtp.rcpttodomain=gmail.com smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none (0)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=kMnGmS0HCMjRP2HhtDMiezX11p9ZCg3sxc+q8fGzVIE=;\n b=DKAhz2jFfzBMpmzkCN4E9BoQdjQM3Mv1Mxcl5Nwx+VbbSiuJIuPIcZvG8IhO8A7INpzq/qqBhqSxel+yYvS3ycBuW8hhlayLgqLicmr1hZ8L2J1LTgcXX1ipw7HF+ioW0V5p/C6rgpyUtuj1L+QerilftiSnx+V7dgP3m09fFgdE8q1byaSAMq31aQE8K9G06BVHIMc945eBU4dH1LpqjiCApHpkFP7q/n6AijTq/odKBB16DjVi1qOrBMj9UPBNzhTxN/Pyz95btLrRK6wVFjq+y68x8SF7Ntba/ik8WrzgLPNxvCLOnaI8TEBav6H9iw7Y0o6Gn9oSaTl8HH0C0Q==","X-MS-Exchange-Authentication-Results":"spf=pass (sender IP is 216.228.118.233)\n smtp.mailfrom=nvidia.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;","Received-SPF":"Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.118.233 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C","From":"Sheetal ","To":"Liam Girdwood , Mark Brown ,\n\tThierry Reding , Jonathan Hunter\n\t","CC":"Jaroslav Kysela , Takashi Iwai , \"Mohan\n Kumar\" , Kuninori Morimoto\n\t, ,\n\t, , Sheetal\n\t","Subject":"[PATCH v3 09/14] ASoC: tegra: Use dev_err_probe() in OPE,\n PEQ and MBDRC drivers","Date":"Wed, 25 Mar 2026 10:14:32 +0000","Message-ID":"<20260325101437.3059693-10-sheetal@nvidia.com>","X-Mailer":"git-send-email 2.17.1","In-Reply-To":"<20260325101437.3059693-1-sheetal@nvidia.com>","References":"<20260325101437.3059693-1-sheetal@nvidia.com>","Precedence":"bulk","X-Mailing-List":"linux-tegra@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain","X-NV-OnPremToCloud":"ExternallySecured","X-EOPAttributedMessage":"0","X-MS-PublicTrafficType":"Email","X-MS-TrafficTypeDiagnostic":"BL02EPF00021F6E:EE_|CH1PPFC908D89D1:EE_","X-MS-Office365-Filtering-Correlation-Id":"9c0130c6-2a7d-4c47-f554-08de8a5775b5","X-MS-Exchange-SenderADCheck":"1","X-MS-Exchange-AntiSpam-Relay":"0","X-Microsoft-Antispam":"\n\tBCL:0;ARA:13230040|36860700016|1800799024|82310400026|376014|22082099003|18002099003|56012099003;","X-Microsoft-Antispam-Message-Info":"\n\tLcSDtlPShprDzY2UxDVLVTkmKu1lmOlbzjvoHUzwxr1IWqW/k7U/mX6wH6OUy4pXLLgOvO7vEv8K1Y/yWI12QE9yVodDlcGWU5v2XxXFumrBp1QWxy5JG6700T/o8pAoggW8pvAPX4FMBPdIiJi9x1dNC2oaoyq539pG7v4f8yAnJg/Fbqdg6qPU90fyALpXSwF87YnTUJ+5WtRysh5VJYLw10eNuAlZUiPs09f1I3oVkur9rfQv4PFaQa7QYxCIGOJ4A1dzFTmhF6PNxekZ/ICU8uMPQsIavZznFSWLW2bpftKo1RoG/P5fdSyfYOz+nXxJn0wQfZ1KEP3PeVggt2adVO4fb5tprT4FPcJB0OVaqGYyqaAljob5uEsj6EpDNYm4Tur8B585s2o6r4TKR82xoK9IclmxTPKD8BfGUlwwUcLJRToIt80qYtYjkL4NKht3Goz5dLwnrUZ4lA8GdoXNhk4KznHx8ZohN7dN35p3KLqI5LgCD1FlNRUfZd3TNkpDgFv357aIfaUzJNdOXxW1mb8PjXsjMshtmUDKuYgT+Y/Y7+H6QeIOK3BWqjaCL9MgCuDsBJD9A+JFaYkBcMAuahnuqjl6bRpz0Ax/1AvZ8GCGxHmvT07haHOMIz88h8Oiul43oTf270X4q9KUhMv82NUURVJLXYPoasIQMRUg8DzdfJDMBmYLPWflNIIzx1PpoeTeT4l+VCMntwEI89xJGxqHrZEWjJfbkd6a7m5uu7KbZzxKc+ohtIS2389UtDV89Cej6Aym4iZPk9rEYQ==","X-Forefront-Antispam-Report":"\n\tCIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(1800799024)(82310400026)(376014)(22082099003)(18002099003)(56012099003);DIR:OUT;SFP:1101;","X-MS-Exchange-AntiSpam-MessageData-ChunkCount":"1","X-MS-Exchange-AntiSpam-MessageData-0":"\n\t+T4oTBfAeTtQYJ8D5OlfkkBowUfdTPBsoz/DQvxXBJcCzj5/2a5QCC26c1pUFv2rBK3qeGt12TpmgcqCRvq4GrMSaiP8GJ5t9uPq+MnwU6Duw1MyyD5+mfBvVmII9S8ekm6kKwTLaUc95CUqzRWFniz1CV29BL4/5WII8Mf/OhKEQMAp+pgVEQLXtFrdthQ5m4+LrIOD8XUvN6/H4+Y4XjLGi83rCT+y0CQ5nmf1I3G4e3e2YtojU0CDoiRy+tfq6H8pgb1rMkI3wAYWY4W+0E7F1j763LegkHjNnnx6DrBJpTSGcpgu93gNm1018wiBMYGch/gfrRZ+laLkq6A7axZxrGnAZkH/Xb8mnR29AKdXwel/gGJEy4QSClh7hFOz50KM7jNPlQoSh/bkOxLw+8XCMD3Z7wzvTkv/ujkOnYAAHNj2RCbgyZxiw2AOBut+","X-OriginatorOrg":"Nvidia.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"25 Mar 2026 10:15:37.3029\n (UTC)","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 9c0130c6-2a7d-4c47-f554-08de8a5775b5","X-MS-Exchange-CrossTenant-Id":"43083d15-7273-40c1-b7db-39efd9ccc17a","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n\tBL02EPF00021F6E.namprd02.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"CH1PPFC908D89D1"},"content":"Log errors in the Tegra210 OPE, PEQ and MBDRC probe paths using\ndev_err_probe().\n\nSigned-off-by: Sheetal \n---\n sound/soc/tegra/tegra210_mbdrc.c | 10 +++++-----\n sound/soc/tegra/tegra210_ope.c | 19 ++++++++-----------\n sound/soc/tegra/tegra210_peq.c | 10 +++++-----\n 3 files changed, 18 insertions(+), 21 deletions(-)","diff":"diff --git a/sound/soc/tegra/tegra210_mbdrc.c b/sound/soc/tegra/tegra210_mbdrc.c\nindex 6a268dbb7197..558b7a21b0be 100644\n--- a/sound/soc/tegra/tegra210_mbdrc.c\n+++ b/sound/soc/tegra/tegra210_mbdrc.c\n@@ -987,8 +987,9 @@ int tegra210_mbdrc_regmap_init(struct platform_device *pdev)\n \tint err;\n \n \tchild = of_get_child_by_name(dev->of_node, \"dynamic-range-compressor\");\n \tif (!child)\n-\t\treturn -ENODEV;\n+\t\treturn dev_err_probe(dev, -ENODEV,\n+\t\t\t\t \"missing 'dynamic-range-compressor' DT child node\\n\");\n \n \terr = of_address_to_resource(child, 0, &mem);\n \tof_node_put(child);\n@@ -1004,7 +1005,6 @@ int tegra210_mbdrc_regmap_init(struct platform_device *pdev)\n \tope->mbdrc_regmap = devm_regmap_init_mmio(dev, regs,\n \t\t\t\t\t\t &tegra210_mbdrc_regmap_cfg);\n-\tif (IS_ERR(ope->mbdrc_regmap)) {\n-\t\tdev_err(dev, \"regmap init failed\\n\");\n-\t\treturn PTR_ERR(ope->mbdrc_regmap);\n-\t}\n+\tif (IS_ERR(ope->mbdrc_regmap))\n+\t\treturn dev_err_probe(dev, PTR_ERR(ope->mbdrc_regmap),\n+\t\t\t\t \"MBDRC regmap init failed\\n\");\n \ndiff --git a/sound/soc/tegra/tegra210_ope.c b/sound/soc/tegra/tegra210_ope.c\nindex a440888dcdbd..e311de41a078 100644\n--- a/sound/soc/tegra/tegra210_ope.c\n+++ b/sound/soc/tegra/tegra210_ope.c\n@@ -329,23 +329,18 @@ static int tegra210_ope_probe(struct platform_device *pdev)\n \n \terr = tegra210_peq_regmap_init(pdev);\n-\tif (err < 0) {\n-\t\tdev_err(dev, \"PEQ init failed\\n\");\n-\t\treturn err;\n-\t}\n+\tif (err < 0)\n+\t\treturn dev_err_probe(dev, err, \"PEQ init failed\\n\");\n \n \terr = tegra210_mbdrc_regmap_init(pdev);\n-\tif (err < 0) {\n-\t\tdev_err(dev, \"MBDRC init failed\\n\");\n-\t\treturn err;\n-\t}\n+\tif (err < 0)\n+\t\treturn dev_err_probe(dev, err, \"MBDRC init failed\\n\");\n \n \terr = devm_snd_soc_register_component(dev, &tegra210_ope_cmpnt,\n \t\t\t\t\t tegra210_ope_dais,\n \t\t\t\t\t ARRAY_SIZE(tegra210_ope_dais));\n-\tif (err) {\n-\t\tdev_err(dev, \"can't register OPE component, err: %d\\n\", err);\n-\t\treturn err;\n-\t}\n+\tif (err)\n+\t\treturn dev_err_probe(dev, err,\n+\t\t\t\t \"can't register OPE component\\n\");\n \n \tpm_runtime_enable(dev);\n \ndiff --git a/sound/soc/tegra/tegra210_peq.c b/sound/soc/tegra/tegra210_peq.c\nindex 2f72e9d541dc..4b692c2055bc 100644\n--- a/sound/soc/tegra/tegra210_peq.c\n+++ b/sound/soc/tegra/tegra210_peq.c\n@@ -407,8 +407,9 @@ int tegra210_peq_regmap_init(struct platform_device *pdev)\n \tint err;\n \n \tchild = of_get_child_by_name(dev->of_node, \"equalizer\");\n \tif (!child)\n-\t\treturn -ENODEV;\n+\t\treturn dev_err_probe(dev, -ENODEV,\n+\t\t\t\t \"missing 'equalizer' DT child node\\n\");\n \n \terr = of_address_to_resource(child, 0, &mem);\n \tof_node_put(child);\n@@ -424,7 +425,6 @@ int tegra210_peq_regmap_init(struct platform_device *pdev)\n \tope->peq_regmap = devm_regmap_init_mmio(dev, regs,\n \t\t\t\t\t\t&tegra210_peq_regmap_config);\n-\tif (IS_ERR(ope->peq_regmap)) {\n-\t\tdev_err(dev, \"regmap init failed\\n\");\n-\t\treturn PTR_ERR(ope->peq_regmap);\n-\t}\n+\tif (IS_ERR(ope->peq_regmap))\n+\t\treturn dev_err_probe(dev, PTR_ERR(ope->peq_regmap),\n+\t\t\t\t \"PEQ regmap init failed\\n\");\n \n","prefixes":["v3","09/14"]}