{"id":2215734,"url":"http://patchwork.ozlabs.org/api/patches/2215734/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/cc3b3b97-90c7-4a1e-9a9d-60364657f932@linux.ibm.com/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2026-03-25T08:53:21","name":"[V2] rs6000: Fix [su]mul_highpart patterns to use unspec [PR122665]","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"e9f1b210d07163e59a5e753479abb17841254541","submitter":{"id":88218,"url":"http://patchwork.ozlabs.org/api/people/88218/?format=json","name":"jeevitha","email":"jeevitha@linux.ibm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/cc3b3b97-90c7-4a1e-9a9d-60364657f932@linux.ibm.com/mbox/","series":[{"id":497396,"url":"http://patchwork.ozlabs.org/api/series/497396/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=497396","date":"2026-03-25T08:53:21","name":"[V2] rs6000: Fix [su]mul_highpart patterns to use unspec [PR122665]","version":2,"mbox":"http://patchwork.ozlabs.org/series/497396/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2215734/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2215734/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=IkcLk1nG;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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charset=UTF-8","Content-Transfer-Encoding":"7bit","X-TM-AS-GCONF":"00","X-Proofpoint-GUID":"Bwwv825AvPra05OpgozC-z5lQ3MBk2It","X-Proofpoint-ORIG-GUID":"Bwwv825AvPra05OpgozC-z5lQ3MBk2It","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwMzI1MDA2MiBTYWx0ZWRfX5qGy5zcbNdEX\n 256xqtttNGCIVjZjeoa4HejGyy1aOGrIQnfGnLD10LH64aUsIYek/RBrHONDBbiwh1RynMAA35L\n 22PNmqv8b2euA1wQVkvKCzm9Om0KnCiP+6FPne/qr17xGPds1hGn8PlCuaZfz/DyJJAXbwkF8sC\n rKLJ31K+0ey3tvumB1QsyBsI6pbOSFyZ+Q2151Et3qsnDwKoWhGUtGI2gbVMxNhVdQllIF6ZCPM\n nvI7gvzegqJJKrQpK77+I2UB+7SFt5k4F9e8QVCHYMFPmRuwDlY0qDgmuEUjex0vkM5LVwDTdKN\n z/H8zXvuwNDYKEsPAZevlBLtXAt7FwDIjpauhEdiK8U1rOXwgSxWf1GhxssXJtaXzTgNDOex5of\n v/LG+bPom8immFt0kXRVM/y0/LwkHFcAB5B7AA63bEgBRZJB2NR3/uQjGyyT+wYF5sGH7eRF+o3\n UmRtNAQnpaRAOCtwTuA==","X-Authority-Analysis":"v=2.4 cv=KbXfcAYD c=1 sm=1 tr=0 ts=69c3a287 cx=c_pps\n a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17\n a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=RnoormkPH1_aCDwRdu11:22 a=RzCfie-kr_QcCd8fBx8p:22 a=VnNF1IyMAAAA:8\n a=Ef7soKIlfam-QSBKTVMA:9 a=QEXdDO2ut3YA:10","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-03-25_03,2026-03-24_01,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n suspectscore=0 impostorscore=0 malwarescore=0 adultscore=0 clxscore=1015\n priorityscore=1501 bulkscore=0 lowpriorityscore=0 phishscore=0 spamscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603250062","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"Hi All,\n\nThe following patch is to fix PR122665 has been bootstrapped and regtested on\npowerpc64le-linux.\n\nChanges from V1:\n * Moved the unspec declarations from vsx.md to rs6000.md, as these\n will be reused in future RFC implementation.\n\nrs6000: Fix [su]mul_highpart patterns to use unspec [PR122665]\n\nThe existing smul3_highpart and umul3_highpart patterns\nincorrectly defined the high-part multiply by shifting both operands\nbefore multiplication. This does not match the semantics of the\ninstructions vmulhs and vmulhu, which perform a widened\nmultiplication and then return the high part.\n\nThis patch replaces the incorrect patterns with UNSPEC_VMULHS and\nUNSPEC_VMULHU forms, and updates the predicate to use\naltivec_register_operand, since these instructions accept only\nAltivec registers.\n\n2025-03-25 Jeevitha Palanisamy \n\ngcc/\n\tPR target/122665\n\t* config/rs6000/rs6000.md (UNSPEC_VMULHS, UNSPEC_VMULHU): New.\n\t* config/rs6000/vsx.md (smul3_highpart): Use UNSPEC_VMULHS.\n\t(umul3_highpart): Use UNSPEC_VMULHU.","diff":"diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md\nindex 3089551552c..a5481df6880 100644\n--- a/gcc/config/rs6000/rs6000.md\n+++ b/gcc/config/rs6000/rs6000.md\n@@ -173,6 +173,8 @@\n UNSPEC_XXSPLTIW_CONST\n UNSPEC_FMAX\n UNSPEC_FMIN\n+ UNSPEC_VMULHS\n+ UNSPEC_VMULHU\n ])\n \n ;;\ndiff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md\nindex cfad9b8c6d5..f4979e447de 100644\n--- a/gcc/config/rs6000/vsx.md\n+++ b/gcc/config/rs6000/vsx.md\n@@ -6547,25 +6547,19 @@\n (set_attr \"size\" \"\")])\n \n (define_insn \"smul3_highpart\"\n- [(set (match_operand:VIlong 0 \"vsx_register_operand\" \"=v\")\n-\t(mult:VIlong (ashiftrt\n-\t\t (match_operand:VIlong 1 \"vsx_register_operand\" \"v\")\n-\t\t (const_int 32))\n-\t\t (ashiftrt\n-\t\t (match_operand:VIlong 2 \"vsx_register_operand\" \"v\")\n-\t\t (const_int 32))))]\n+ [(set (match_operand:VIlong 0 \"altivec_register_operand\" \"=v\")\n+ (unspec:VIlong [(match_operand:VIlong 1 \"altivec_register_operand\" \"v\")\n+ (match_operand:VIlong 2 \"altivec_register_operand\" \"v\")]\n+ UNSPEC_VMULHS))]\n \"TARGET_POWER10\"\n \"vmulhs %0,%1,%2\"\n [(set_attr \"type\" \"veccomplex\")])\n \n (define_insn \"umul3_highpart\"\n- [(set (match_operand:VIlong 0 \"vsx_register_operand\" \"=v\")\n-\t(us_mult:VIlong (ashiftrt\n-\t\t\t (match_operand:VIlong 1 \"vsx_register_operand\" \"v\")\n-\t\t\t (const_int 32))\n-\t\t\t(ashiftrt\n-\t\t\t (match_operand:VIlong 2 \"vsx_register_operand\" \"v\")\n-\t\t\t (const_int 32))))]\n+ [(set (match_operand:VIlong 0 \"altivec_register_operand\" \"=v\")\n+ (unspec:VIlong [(match_operand:VIlong 1 \"altivec_register_operand\" \"v\")\n+ (match_operand:VIlong 2 \"altivec_register_operand\" \"v\")]\n+ UNSPEC_VMULHU))]\n \"TARGET_POWER10\"\n \"vmulhu %0,%1,%2\"\n [(set_attr \"type\" \"veccomplex\")])\n","prefixes":["V2"]}