{"id":2215714,"url":"http://patchwork.ozlabs.org/api/patches/2215714/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/177442359063.1954.8266696018975379698-0@git.sr.ht/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<177442359063.1954.8266696018975379698-0@git.sr.ht>","list_archive_url":null,"date":"2026-03-25T06:31:56","name":"[qemu] hw/intc: Call sifive_plic_update() after writing interrupt enable","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"712f316128df0994d22f80c7949f1e98173a36e5","submitter":{"id":88853,"url":"http://patchwork.ozlabs.org/api/people/88853/?format=json","name":"~liuxu","email":"liuxu@git.sr.ht"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/177442359063.1954.8266696018975379698-0@git.sr.ht/mbox/","series":[{"id":497389,"url":"http://patchwork.ozlabs.org/api/series/497389/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497389","date":"2026-03-25T06:31:56","name":"[qemu] hw/intc: Call sifive_plic_update() after writing interrupt enable","version":1,"mbox":"http://patchwork.ozlabs.org/series/497389/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2215714/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2215714/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=fail reason=\"key not found in DNS\" header.d=git.sr.ht\n header.i=@git.sr.ht header.a=rsa-sha256 header.s=20240113 header.b=Nnc2SHOu;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fgdlT4Jtbz1xy3\n\tfor ; Wed, 25 Mar 2026 18:27:16 +1100 (AEDT)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1w5IdY-0000Vd-FC; Wed, 25 Mar 2026 03:26:44 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from ) id 1w5IdS-0000UQ-VB\n for qemu-devel@nongnu.org; Wed, 25 Mar 2026 03:26:38 -0400","from mail-a.sr.ht ([46.23.81.152])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from ) id 1w5IdP-00042G-IC\n for qemu-devel@nongnu.org; Wed, 25 Mar 2026 03:26:38 -0400","from git.sr.ht (unknown [46.23.81.155])\n by mail-a.sr.ht (Postfix) with ESMTPSA id A6A0A204D3;\n Wed, 25 Mar 2026 07:26:30 +0000 (UTC)"],"DKIM-Signature":"a=rsa-sha256; bh=HZ75dORxjIw1V8rr7cp27pcFAphouxw/JWwEuEBTdgw=;\n c=simple/simple; d=git.sr.ht;\n h=From:Date:Subject:Reply-to:To:Cc;\n q=dns/txt; s=20240113; t=1774423590; v=1;\n b=Nnc2SHOuNWrpJIP7lwVV8rDw2k07ie1mAMCaWHE3qqsoexlMIiXmktqz2OwJ7qYmTbzrtQ77\n rLjQP51JWG/CKyM5wrLGYhcSfpEk1M8u5yu+H5h+21O+fv0yJeBOAmlFIuhKZhpzKb4tmxuwTMg\n ES4KHe6c3XWLZfxix+2dSFbc49JWb7FT7dTq/1lscdiahahbd2OLtl936TgFPe6miz/RThjL9dn\n ppE8m4v5aPZ2OcpVVEJ6q51yAxjoIlNXb5R2Em9nPZJEKA3iMgxONbReJiUq1SJDTEe1V/pRUdX\n X+Lei4dRMCQZTwId2aSGGj9SJ68GvGxN4cCfjP3Zx2GPA==","From":"~liuxu ","Date":"Wed, 25 Mar 2026 14:31:56 +0800","Subject":"[PATCH qemu] hw/intc: Call sifive_plic_update() after writing\n interrupt enable","Message-ID":"<177442359063.1954.8266696018975379698-0@git.sr.ht>","X-Mailer":"git.sr.ht","To":"qemu-devel@nongnu.org","Cc":"Richard Henderson ","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"quoted-printable","MIME-Version":"1.0","Received-SPF":"pass client-ip=46.23.81.152; envelope-from=outgoing@sr.ht;\n helo=mail-a.sr.ht","X-Spam_score_int":"-16","X-Spam_score":"-1.7","X-Spam_bar":"-","X-Spam_report":"(-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1,\n DKIM_SIGNED=0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Reply-To":"~liuxu ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: lxx <1733205434@qq.com>\n\nWhen a guest writes to the interrupt enable register, the PLIC state\nis updated but sifive_plic_update() is not called to re-evaluate the\ninterrupt line to the hart. This causes a lost interrupt when the\npending bit is set before the enable bit is written.\n\nThis is a level-triggered condition that must be re-evaluated whenever\nany of the three factors change: pending bits, enable bits, or\nthreshold/priority. All other register writes that affect interrupt\ndelivery (priority, pending, threshold) already call\nsifive_plic_update() after the write. Fix the enable register write\nhandler to do the same.\n\nSigned-off-by: LIU Xu \n---\n hw/intc/sifive_plic.c | 1 +\n 1 file changed, 1 insertion(+)","diff":"diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c\nindex 9c84ff06a9f..f893384e4df 100644\n--- a/hw/intc/sifive_plic.c\n+++ b/hw/intc/sifive_plic.c\n@@ -219,6 +219,7 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,\n \n if (wordid < plic->bitfield_words) {\n plic->enable[addrid * plic->bitfield_words + wordid] = value;\n+ sifive_plic_update(plic);\n } else {\n qemu_log_mask(LOG_GUEST_ERROR,\n \"%s: Invalid enable write 0x%\" HWADDR_PRIx \"\\n\",\n","prefixes":["qemu"]}