{"id":2215709,"url":"http://patchwork.ozlabs.org/api/patches/2215709/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/ce3c44f3b07734a4f0ee43f55b21c856034af1b1.1774421649.git.15fengyuan@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2026-03-25T07:09:06","name":"[v3,2/2] tests/qtest: Add Intel IOMMU bare-metal test","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"8dbed829532993557938cdbfaab7301ba48a79f7","submitter":{"id":92576,"url":"http://patchwork.ozlabs.org/api/people/92576/?format=json","name":"Fengyuan Yu","email":"15fengyuan@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/ce3c44f3b07734a4f0ee43f55b21c856034af1b1.1774421649.git.15fengyuan@gmail.com/mbox/","series":[{"id":497387,"url":"http://patchwork.ozlabs.org/api/series/497387/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497387","date":"2026-03-25T07:09:04","name":"tests/qtest: Add Intel IOMMU bare-metal test using iommu-testdev","version":3,"mbox":"http://patchwork.ozlabs.org/series/497387/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2215709/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2215709/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=al5bt+UW;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fgdMw5C4Lz1xy3\n\tfor ; Wed, 25 Mar 2026 18:10:20 +1100 (AEDT)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1w5INA-0005EN-E0; Wed, 25 Mar 2026 03:09:48 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <15fengyuan@gmail.com>)\n id 1w5IN9-0005ED-BC\n for qemu-devel@nongnu.org; Wed, 25 Mar 2026 03:09:47 -0400","from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <15fengyuan@gmail.com>)\n id 1w5IN7-0001MP-7J\n for qemu-devel@nongnu.org; Wed, 25 Mar 2026 03:09:47 -0400","by mail-pj1-x102e.google.com with SMTP id\n 98e67ed59e1d1-35c05d7e0e9so1303087a91.1\n for ; Wed, 25 Mar 2026 00:09:44 -0700 (PDT)","from orion-o6.tail020997.ts.net ([2408:8352:441:f661::1002])\n by smtp.gmail.com with ESMTPSA id\n 98e67ed59e1d1-35c031354f3sm5328074a91.6.2026.03.25.00.09.40\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Wed, 25 Mar 2026 00:09:43 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=gmail.com; s=20251104; t=1774422584; x=1775027384; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=/NYQMO/wLuGmsvFvoRe4026atOOoo2S8nwbhA7znUx8=;\n b=al5bt+UWB/C9z1CrYJomEIaC8FjhQRzb2JUJkKVPap3Sd9fvTxp11Y4SxOObp39dx9\n OsThk/RaZOsnPtbJoV4lZ6V4S4CItUf0fHTX4dRi36mLVMUbp8SIl0fu4IhnOs6JZKAj\n qpVtxjI5F3BfXiEICOArGQBBMArFaKO3uTxaWlr25E6GWOp/0prx4ThioA+/mvFr2V1R\n VF83YcrYmduxZ+c5Uj523miEpz1vBzSNsvt91r60txPUAznknt1KBHbB8g0jEDXJ5FsV\n gkmhiknB0NaYUlRK/hy8hwl2lEoIlQTJISKo6p8uxmXnuM5wul1zC8gN7VoBdQUXYJoP\n uqsA==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1774422584; x=1775027384;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=/NYQMO/wLuGmsvFvoRe4026atOOoo2S8nwbhA7znUx8=;\n b=Z2ANCdTiiTbihXJ2hh+xTTOim11wv3LdIi+QmPDGzl1/Sgk7PyKO9WhGhFltHb7poI\n h+ifH4SE7xjlf6ItXc9onkyyYkKkq7iejHv74UuqwjJZ4+UMEp5kfNE6uM4220ZK+2WT\n uWvchdWftLdhQKs/EGcgcBDg6khhRbZ7nMars1k0a8AfFYLEcEAMqPaa8j9rs7dqqNBJ\n /b87dVOlvNji8XEJKgWn/3+1EtXjb84VGXMcHDK3Dy6FwgSHERoaUfEtFWX5s8HIDJvd\n weyr7vsKFCZHd6LvagD1/AZFMkLqwOZhzvV8zKLWx8RsxGT2WriofTC7XKtZWZ12KOVf\n LaBA==","X-Gm-Message-State":"AOJu0Yytr43TaB2DhwSHgygRpcgvMP33BWvY9DjDpqlKuniGbLMEdQAk\n Za/n5CmWE2yBg2Ex9kBtvioyLKLQw7NKL3MBl8RPhGJCuaZbNkeD3h6o","X-Gm-Gg":"ATEYQzzVbYKFft0PSrWD0CssTCemWpZXhoEUFIn2kWasDMqHW1l7M0nO3YRdnxUsU5h\n urTxhAthcDYxlYf2gB+7B43H3n5+dbYnveo1pKCTOHz9+ZKkTygdqcuOHeWIaUX/lCi9sosAdAl\n o7cTvR3NQk/cZDGsfA9CRGqtK+0AspwvPQoFvr71RCK2VaWl2nmNgQFgqN1vIEawSA6taOhBRW3\n nNkv+GFWPoOgxkyWyWjQzpxr2rqYIBY0m/PePJayiCxigmrx5/1oHU8DLUWK5YJN5vr8V9PLl7j\n sxAfd6z4wLwocD9aDOqE5y+y1p82DkzUfAAaF902Fp1KL+BXjU1iJq1Yp/lgI5xrIDPDBUgFhUj\n Z66U6snb1etkohuIpwVLWgoPIdGN6DVl2byMsU9aQZanWZYJJbEZUXZ/4sUlc+yaIe/LZNzRrlb\n F6fxc0xwcllMcG/Rv89E57T14iuZk=","X-Received":"by 2002:a17:90b:3a92:b0:343:7714:4ca8 with SMTP id\n 98e67ed59e1d1-35c0dcacb27mr2149544a91.15.1774422583603;\n Wed, 25 Mar 2026 00:09:43 -0700 (PDT)","From":"Fengyuan Yu <15fengyuan@gmail.com>","To":"\"Michael S. Tsirkin\" , Jason Wang ,\n Yi Liu ,\n =?utf-8?q?Cl=C3=A9ment_Mathieu--Drif?= ,\n Fabiano Rosas , Laurent Vivier ,\n Paolo Bonzini , Tao Tang ","Cc":"qemu-devel@nongnu.org, Chao Liu ,\n Fengyuan Yu <15fengyuan@gmail.com>","Subject":"[PATCH v3 2/2] tests/qtest: Add Intel IOMMU bare-metal test","Date":"Wed, 25 Mar 2026 15:09:06 +0800","Message-Id":"\n ","X-Mailer":"git-send-email 2.39.5","In-Reply-To":"","References":"","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::102e;\n envelope-from=15fengyuan@gmail.com; helo=mail-pj1-x102e.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Add a qtest suite for the Intel IOMMU (VT-d) device on the Q35 machine.\nThe test exercises both Legacy and Scalable translation modes using\niommu-testdev and the qos-intel-iommu helpers, without requiring any\nguest kernel or firmware.\n\nThe test validates:\n- Legacy-mode Root Entry Table and Context Entry Table configuration\n- Scalable-mode Context Entry, PASID Directory, and PASID Table setup\n- Legacy-mode 4-level page table walks for 48-bit address translation\n- Scalable-mode second-level and first-level 4-level page table walks\n- Pass-through mode in both Legacy and Scalable modes\n- DMA transaction execution with memory content verification\n\nReviewed-by: Chao Liu \nSigned-off-by: Fengyuan Yu <15fengyuan@gmail.com>\n---\n MAINTAINERS | 1 +\n tests/qtest/iommu-intel-test.c | 216 +++++++++++++++++++++++++++++++++\n tests/qtest/meson.build | 2 +\n 3 files changed, 219 insertions(+)\n create mode 100644 tests/qtest/iommu-intel-test.c","diff":"diff --git a/MAINTAINERS b/MAINTAINERS\nindex ba0901bf4f..420f7ab6cf 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -4016,6 +4016,7 @@ F: hw/i386/intel_iommu_accel.*\n F: include/hw/i386/intel_iommu.h\n F: tests/functional/x86_64/test_intel_iommu.py\n F: tests/qtest/intel-iommu-test.c\n+F: tests/qtest/iommu-intel-test.c\n \n AMD-Vi Emulation\n M: Alejandro Jimenez \ndiff --git a/tests/qtest/iommu-intel-test.c b/tests/qtest/iommu-intel-test.c\nnew file mode 100644\nindex 0000000000..a52c45e298\n--- /dev/null\n+++ b/tests/qtest/iommu-intel-test.c\n@@ -0,0 +1,216 @@\n+/*\n+ * QTest for Intel IOMMU (VT-d) with iommu-testdev\n+ *\n+ * This QTest file is used to test the Intel IOMMU with iommu-testdev so that\n+ * we can test VT-d without any guest kernel or firmware.\n+ *\n+ * Copyright (c) 2026 Fengyuan Yu <15fengyuan@gmail.com>\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"libqtest.h\"\n+#include \"libqos/pci.h\"\n+#include \"libqos/pci-pc.h\"\n+#include \"hw/i386/intel_iommu_internal.h\"\n+#include \"hw/misc/iommu-testdev.h\"\n+#include \"libqos/qos-intel-iommu.h\"\n+\n+#define DMA_LEN 4\n+\n+static uint64_t intel_iommu_expected_gpa(uint64_t iova)\n+{\n+ return (QVTD_PT_VAL & VTD_PAGE_MASK_4K) + (iova & 0xfff);\n+}\n+\n+static void save_fn(QPCIDevice *dev, int devfn, void *data)\n+{\n+ QPCIDevice **pdev = (QPCIDevice **) data;\n+\n+ *pdev = dev;\n+}\n+\n+static QPCIDevice *setup_qtest_pci_device(QTestState *qts, QPCIBus **pcibus,\n+ QPCIBar *bar)\n+{\n+ QPCIDevice *dev = NULL;\n+\n+ *pcibus = qpci_new_pc(qts, NULL);\n+ g_assert(*pcibus != NULL);\n+\n+ qpci_device_foreach(*pcibus, IOMMU_TESTDEV_VENDOR_ID,\n+ IOMMU_TESTDEV_DEVICE_ID, save_fn, &dev);\n+\n+ g_assert(dev);\n+ qpci_device_enable(dev);\n+ *bar = qpci_iomap(dev, 0, NULL);\n+ g_assert_false(bar->is_io);\n+\n+ return dev;\n+}\n+\n+static const char *qvtd_iommu_args(QVTDTransMode mode)\n+{\n+ switch (mode) {\n+ case QVTD_TM_SCALABLE_FLT:\n+ return \"-device intel-iommu,x-scalable-mode=on,x-flts=on \";\n+ case QVTD_TM_SCALABLE_PT:\n+ case QVTD_TM_SCALABLE_SLT:\n+ return \"-device intel-iommu,x-scalable-mode=on \";\n+ default:\n+ return \"-device intel-iommu \";\n+ }\n+}\n+\n+static bool qvtd_check_caps(QTestState *qts, QVTDTransMode mode)\n+{\n+ uint64_t ecap = qtest_readq(qts,\n+ Q35_HOST_BRIDGE_IOMMU_ADDR + DMAR_ECAP_REG);\n+\n+ /* All scalable modes require SMTS */\n+ if (qvtd_is_scalable(mode) && !(ecap & VTD_ECAP_SMTS)) {\n+ g_test_skip(\"ECAP.SMTS not supported\");\n+ return false;\n+ }\n+\n+ switch (mode) {\n+ case QVTD_TM_SCALABLE_PT:\n+ if (!(ecap & VTD_ECAP_PT)) {\n+ g_test_skip(\"ECAP.PT not supported\");\n+ return false;\n+ }\n+ break;\n+ case QVTD_TM_SCALABLE_SLT:\n+ if (!(ecap & VTD_ECAP_SSTS)) {\n+ g_test_skip(\"ECAP.SSTS not supported\");\n+ return false;\n+ }\n+ break;\n+ case QVTD_TM_SCALABLE_FLT:\n+ if (!(ecap & VTD_ECAP_FSTS)) {\n+ g_test_skip(\"ECAP.FSTS not supported\");\n+ return false;\n+ }\n+ break;\n+ default:\n+ break;\n+ }\n+\n+ return true;\n+}\n+\n+static void run_intel_iommu_translation(const QVTDTestConfig *cfg)\n+{\n+ QTestState *qts;\n+ QPCIBus *pcibus;\n+ QPCIDevice *dev;\n+ QPCIBar bar;\n+\n+ if (!qtest_has_machine(\"q35\")) {\n+ g_test_skip(\"q35 machine not available\");\n+ return;\n+ }\n+\n+ /* Initialize QEMU environment for Intel IOMMU testing */\n+ qts = qtest_initf(\"-machine q35 -smp 1 -m 512 -net none \"\n+ \"%s -device iommu-testdev\",\n+ qvtd_iommu_args(cfg->trans_mode));\n+\n+ /* Check CAP/ECAP capabilities for required translation mode */\n+ if (!qvtd_check_caps(qts, cfg->trans_mode)) {\n+ qtest_quit(qts);\n+ return;\n+ }\n+\n+ /* Setup and configure IOMMU-testdev PCI device */\n+ dev = setup_qtest_pci_device(qts, &pcibus, &bar);\n+ g_assert(dev);\n+\n+ g_test_message(\"### Intel IOMMU translation mode=%d ###\", cfg->trans_mode);\n+ qvtd_run_translation_case(qts, dev, bar, Q35_HOST_BRIDGE_IOMMU_ADDR, cfg);\n+ g_free(dev);\n+ qpci_free_pc(pcibus);\n+ qtest_quit(qts);\n+}\n+\n+static void test_intel_iommu_legacy_pt(void)\n+{\n+ QVTDTestConfig cfg = {\n+ .trans_mode = QVTD_TM_LEGACY_PT,\n+ .dma_gpa = QVTD_IOVA, /* pass-through: GPA == IOVA */\n+ .dma_len = DMA_LEN,\n+ .expected_result = 0,\n+ };\n+\n+ run_intel_iommu_translation(&cfg);\n+}\n+\n+static void test_intel_iommu_legacy_trans(void)\n+{\n+ QVTDTestConfig cfg = {\n+ .trans_mode = QVTD_TM_LEGACY_TRANS,\n+ .dma_gpa = intel_iommu_expected_gpa(QVTD_IOVA),\n+ .dma_len = DMA_LEN,\n+ .expected_result = 0,\n+ };\n+\n+ run_intel_iommu_translation(&cfg);\n+}\n+\n+static void test_intel_iommu_scalable_pt(void)\n+{\n+ QVTDTestConfig cfg = {\n+ .trans_mode = QVTD_TM_SCALABLE_PT,\n+ .dma_gpa = QVTD_IOVA, /* pass-through: GPA == IOVA */\n+ .dma_len = DMA_LEN,\n+ .expected_result = 0,\n+ };\n+\n+ run_intel_iommu_translation(&cfg);\n+}\n+\n+static void test_intel_iommu_scalable_slt(void)\n+{\n+ QVTDTestConfig cfg = {\n+ .trans_mode = QVTD_TM_SCALABLE_SLT,\n+ .dma_gpa = intel_iommu_expected_gpa(QVTD_IOVA),\n+ .dma_len = DMA_LEN,\n+ .expected_result = 0,\n+ };\n+\n+ run_intel_iommu_translation(&cfg);\n+}\n+\n+static void test_intel_iommu_scalable_flt(void)\n+{\n+ QVTDTestConfig cfg = {\n+ .trans_mode = QVTD_TM_SCALABLE_FLT,\n+ .dma_gpa = intel_iommu_expected_gpa(QVTD_IOVA),\n+ .dma_len = DMA_LEN,\n+ .expected_result = 0,\n+ };\n+\n+ run_intel_iommu_translation(&cfg);\n+}\n+\n+int main(int argc, char **argv)\n+{\n+ g_test_init(&argc, &argv, NULL);\n+\n+ /* Legacy mode tests */\n+ qtest_add_func(\"/iommu-testdev/intel/legacy-pt\",\n+ test_intel_iommu_legacy_pt);\n+ qtest_add_func(\"/iommu-testdev/intel/legacy-trans\",\n+ test_intel_iommu_legacy_trans);\n+\n+ /* Scalable mode tests */\n+ qtest_add_func(\"/iommu-testdev/intel/scalable-pt\",\n+ test_intel_iommu_scalable_pt);\n+ qtest_add_func(\"/iommu-testdev/intel/scalable-slt\",\n+ test_intel_iommu_scalable_slt);\n+ qtest_add_func(\"/iommu-testdev/intel/scalable-flt\",\n+ test_intel_iommu_scalable_flt);\n+\n+ return g_test_run();\n+}\ndiff --git a/tests/qtest/meson.build b/tests/qtest/meson.build\nindex be4fa627b5..264bce9f81 100644\n--- a/tests/qtest/meson.build\n+++ b/tests/qtest/meson.build\n@@ -96,6 +96,8 @@ qtests_i386 = \\\n (config_all_devices.has_key('CONFIG_SDHCI_PCI') ? ['fuzz-sdcard-test'] : []) + \\\n (config_all_devices.has_key('CONFIG_ESP_PCI') ? ['am53c974-test'] : []) + \\\n (config_all_devices.has_key('CONFIG_VTD') ? ['intel-iommu-test'] : []) + \\\n+ (config_all_devices.has_key('CONFIG_VTD') and\n+ config_all_devices.has_key('CONFIG_IOMMU_TESTDEV') ? ['iommu-intel-test'] : []) + \\\n (host_os != 'windows' and \\\n config_all_devices.has_key('CONFIG_ACPI_ERST') ? ['erst-test'] : []) + \\\n (config_all_devices.has_key('CONFIG_PCIE_PORT') and \\\n","prefixes":["v3","2/2"]}