{"id":2215700,"url":"http://patchwork.ozlabs.org/api/patches/2215700/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260325050011.66722-2-jay.chang@sifive.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260325050011.66722-2-jay.chang@sifive.com>","list_archive_url":null,"date":"2026-03-25T05:00:10","name":"[v2,1/2] hw/riscv/riscv-iommu-hpm: Fix irq_overflow_left residual value bug","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"f347b376714dcda9644cab4c61e9597d788ce63b","submitter":{"id":90508,"url":"http://patchwork.ozlabs.org/api/people/90508/?format=json","name":"Jay Chang","email":"jay.chang@sifive.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260325050011.66722-2-jay.chang@sifive.com/mbox/","series":[{"id":497382,"url":"http://patchwork.ozlabs.org/api/series/497382/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497382","date":"2026-03-25T05:00:10","name":"Bug fixes and IPSR.PMIP support","version":2,"mbox":"http://patchwork.ozlabs.org/series/497382/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2215700/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2215700/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=X7SJY0Bt;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pj1-x102c.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Reset irq_overflow_left to 0 before setting up a new timer. Without\nthis fix, a stale irq_overflow_left value from a previous timer setup\ncould cause incorrect timer behavior.\n\nSigned-off-by: Jay Chang \nReviewed-by: Frank Chang \nReviewed-by: Chao Liu \n---\n hw/riscv/riscv-iommu-hpm.c | 1 +\n 1 file changed, 1 insertion(+)","diff":"diff --git a/hw/riscv/riscv-iommu-hpm.c b/hw/riscv/riscv-iommu-hpm.c\nindex c5034bff79..e8d284ac8b 100644\n--- a/hw/riscv/riscv-iommu-hpm.c\n+++ b/hw/riscv/riscv-iommu-hpm.c\n@@ -228,6 +228,7 @@ static void hpm_setup_timer(RISCVIOMMUState *s, uint64_t value)\n }\n \n overflow_at = (uint64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + overflow_ns;\n+ s->irq_overflow_left = 0;\n \n if (overflow_at > INT64_MAX) {\n s->irq_overflow_left = overflow_at - INT64_MAX;\n","prefixes":["v2","1/2"]}