{"id":2215661,"url":"http://patchwork.ozlabs.org/api/patches/2215661/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260325014856.58948-1-jay.chang@sifive.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260325014856.58948-1-jay.chang@sifive.com>","list_archive_url":null,"date":"2026-03-25T01:48:56","name":"[v2] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"7d945b5c53e70e3def19d5dec0448375d1d5d252","submitter":{"id":90508,"url":"http://patchwork.ozlabs.org/api/people/90508/?format=json","name":"Jay Chang","email":"jay.chang@sifive.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260325014856.58948-1-jay.chang@sifive.com/mbox/","series":[{"id":497374,"url":"http://patchwork.ozlabs.org/api/series/497374/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497374","date":"2026-03-25T01:48:56","name":"[v2] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI","version":2,"mbox":"http://patchwork.ozlabs.org/series/497374/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2215661/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2215661/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=NUeX29a4;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pg1-x52b.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Replace the temporary custom extension bit (TC[32]) with the\nstandard EN_PRI bit defined in RISC-V IOMMU specification.\n\nSigned-off-by: Jay Chang \nReviewed-by: Frank Chang \nReviewed-by: Nutty Liu \n\nChange in V2:\n Align code\n\nSigned-off-by: Jay Chang \n---\n hw/riscv/riscv-iommu.c | 7 ++-----\n 1 file changed, 2 insertions(+), 5 deletions(-)","diff":"diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c\nindex 225394ea83..30343e98d0 100644\n--- a/hw/riscv/riscv-iommu.c\n+++ b/hw/riscv/riscv-iommu.c\n@@ -1572,11 +1572,8 @@ static int riscv_iommu_translate(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,\n riscv_iommu_hpm_incr_ctr(s, ctx, RISCV_IOMMU_HPMEVENT_URQ);\n \n iot_cache = g_hash_table_ref(s->iot_cache);\n- /*\n- * TC[32] is reserved for custom extensions, used here to temporarily\n- * enable automatic page-request generation for ATS queries.\n- */\n- enable_pri = (iotlb->perm == IOMMU_NONE) && (ctx->tc & BIT_ULL(32));\n+ enable_pri = (iotlb->perm == IOMMU_NONE) &&\n+ (ctx->tc & RISCV_IOMMU_DC_TC_EN_PRI);\n enable_pid = (ctx->tc & RISCV_IOMMU_DC_TC_PDTV);\n \n /* Check for ATS request. */\n","prefixes":["v2"]}