{"id":2215572,"url":"http://patchwork.ozlabs.org/api/patches/2215572/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260324191000.1095768-5-mmaddireddy@nvidia.com/","project":{"id":21,"url":"http://patchwork.ozlabs.org/api/projects/21/?format=json","name":"Linux Tegra Development","link_name":"linux-tegra","list_id":"linux-tegra.vger.kernel.org","list_email":"linux-tegra@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260324191000.1095768-5-mmaddireddy@nvidia.com>","list_archive_url":null,"date":"2026-03-24T19:09:55","name":"[v8,4/9] PCI: tegra194: Enable DMA interrupt","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"593f089acf7aa465598365897ff016b4e2635379","submitter":{"id":72399,"url":"http://patchwork.ozlabs.org/api/people/72399/?format=json","name":"Manikanta Maddireddy","email":"mmaddireddy@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260324191000.1095768-5-mmaddireddy@nvidia.com/mbox/","series":[{"id":497332,"url":"http://patchwork.ozlabs.org/api/series/497332/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/list/?series=497332","date":"2026-03-24T19:09:52","name":"Enhancements to pcie-tegra194 driver","version":8,"mbox":"http://patchwork.ozlabs.org/series/497332/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2215572/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2215572/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n 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00:39:55 +0530","Message-ID":"<20260324191000.1095768-5-mmaddireddy@nvidia.com>","X-Mailer":"git-send-email 2.34.1","In-Reply-To":"<20260324191000.1095768-1-mmaddireddy@nvidia.com>","References":"<20260324191000.1095768-1-mmaddireddy@nvidia.com>","Precedence":"bulk","X-Mailing-List":"linux-tegra@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","X-NVConfidentiality":"public","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-ClientProxiedBy":"rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com 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Mar 2026 19:11:07.6041\n (UTC)","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n bf7637e0-1070-4d55-b836-08de89d91a6d","X-MS-Exchange-CrossTenant-Id":"43083d15-7273-40c1-b7db-39efd9ccc17a","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n\tDS2PEPF00003444.namprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"SA1PR12MB6774"},"content":"From: Vidya Sagar \n\nEnable DMA interrupt to support Tegra PCIe DMA in both Root Port and\nEndpoint modes.\n\nReviewed-by: Jon Hunter \nTested-by: Jon Hunter \nSigned-off-by: Vidya Sagar \nSigned-off-by: Manikanta Maddireddy \n---\nChanges V1 -> V8: None\n\n drivers/pci/controller/dwc/pcie-tegra194.c | 14 ++++++++++++++\n 1 file changed, 14 insertions(+)","diff":"diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c\nindex 63173f7af62b..b312d02f8dab 100644\n--- a/drivers/pci/controller/dwc/pcie-tegra194.c\n+++ b/drivers/pci/controller/dwc/pcie-tegra194.c\n@@ -91,6 +91,7 @@\n #define APPL_INTR_EN_L1_8_0\t\t\t0x44\n #define APPL_INTR_EN_L1_8_BW_MGT_INT_EN\t\tBIT(2)\n #define APPL_INTR_EN_L1_8_AUTO_BW_INT_EN\tBIT(3)\n+#define APPL_INTR_EN_L1_8_EDMA_INT_EN\t\tBIT(6)\n #define APPL_INTR_EN_L1_8_INTX_EN\t\tBIT(11)\n #define APPL_INTR_EN_L1_8_AER_INT_EN\t\tBIT(15)\n \n@@ -544,6 +545,13 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg)\n \t\tspurious = 0;\n \t}\n \n+\tif (status_l0 & APPL_INTR_STATUS_L0_INT_INT) {\n+\t\tstatus_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_8_0);\n+\t\t/* Interrupt is handled by dma driver, don't treat it as spurious */\n+\t\tif (status_l1 & APPL_INTR_STATUS_L1_8_0_EDMA_INT_MASK)\n+\t\t\tspurious = 0;\n+\t}\n+\n \tif (spurious) {\n \t\tdev_warn(pcie->dev, \"Random interrupt (STATUS = 0x%08X)\\n\",\n \t\t\t status_l0);\n@@ -779,6 +787,7 @@ static void tegra_pcie_enable_intx_interrupts(struct dw_pcie_rp *pp)\n \tval |= APPL_INTR_EN_L1_8_INTX_EN;\n \tval |= APPL_INTR_EN_L1_8_AUTO_BW_INT_EN;\n \tval |= APPL_INTR_EN_L1_8_BW_MGT_INT_EN;\n+\tval |= APPL_INTR_EN_L1_8_EDMA_INT_EN;\n \tif (IS_ENABLED(CONFIG_PCIEAER))\n \t\tval |= APPL_INTR_EN_L1_8_AER_INT_EN;\n \tappl_writel(pcie, val, APPL_INTR_EN_L1_8_0);\n@@ -1805,6 +1814,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)\n \tval |= APPL_INTR_EN_L0_0_SYS_INTR_EN;\n \tval |= APPL_INTR_EN_L0_0_LINK_STATE_INT_EN;\n \tval |= APPL_INTR_EN_L0_0_PCI_CMD_EN_INT_EN;\n+\tval |= APPL_INTR_EN_L0_0_INT_INT_EN;\n \tappl_writel(pcie, val, APPL_INTR_EN_L0_0);\n \n \tval = appl_readl(pcie, APPL_INTR_EN_L1_0_0);\n@@ -1812,6 +1822,10 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)\n \tval |= APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN;\n \tappl_writel(pcie, val, APPL_INTR_EN_L1_0_0);\n \n+\tval = appl_readl(pcie, APPL_INTR_EN_L1_8_0);\n+\tval |= APPL_INTR_EN_L1_8_EDMA_INT_EN;\n+\tappl_writel(pcie, val, APPL_INTR_EN_L1_8_0);\n+\n \t/* 110us for both snoop and no-snoop */\n \tval = FIELD_PREP(PCI_LTR_VALUE_MASK, 110) |\n \t FIELD_PREP(PCI_LTR_SCALE_MASK, 2) |\n","prefixes":["v8","4/9"]}