{"id":2215555,"url":"http://patchwork.ozlabs.org/api/patches/2215555/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260324190755.1094879-15-mmaddireddy@nvidia.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260324190755.1094879-15-mmaddireddy@nvidia.com>","list_archive_url":null,"date":"2026-03-24T19:07:55","name":"[v8,14/14] PCI: tegra194: Fix CBB timeout caused by DBI access before core power-on","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"f4c6c194004655c55739b152d1459b47d6812055","submitter":{"id":72399,"url":"http://patchwork.ozlabs.org/api/people/72399/?format=json","name":"Manikanta Maddireddy","email":"mmaddireddy@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260324190755.1094879-15-mmaddireddy@nvidia.com/mbox/","series":[{"id":497331,"url":"http://patchwork.ozlabs.org/api/series/497331/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=497331","date":"2026-03-24T19:07:42","name":"Fixes to pcie-tegra194 driver","version":8,"mbox":"http://patchwork.ozlabs.org/series/497331/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2215555/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2215555/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=sNm/xEan;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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This happens because pci_epc_deinit_notify()\nand dw_pcie_ep_cleanup() are called before reset_control_deassert() powers\non the controller core.\n\nThe call chain that causes the timeout:\n pex_ep_event_pex_rst_deassert()\n pci_epc_deinit_notify()\n pci_epf_test_epc_deinit()\n pci_epf_test_clear_bar()\n pci_epc_clear_bar()\n dw_pcie_ep_clear_bar()\n __dw_pcie_ep_reset_bar()\n dw_pcie_dbi_ro_wr_en() <- Accesses 0x8bc DBI register\n reset_control_deassert(pcie->core_rst) <- Core powered on HERE\n\nThe DBI registers, including PCIE_MISC_CONTROL_1_OFF (0x8bc), are only\naccessible after the controller core is powered on via\nreset_control_deassert(pcie->core_rst). Accessing them before this point\nresults in a CBB timeout because the hardware is not yet operational.\n\nFix this by moving pci_epc_deinit_notify() and dw_pcie_ep_cleanup() to\nafter reset_control_deassert(pcie->core_rst), ensuring the controller is\nfully powered on before any DBI register accesses occur.\n\nFixes: 40e2125381dc (\"PCI: tegra194: Move controller cleanups to pex_ep_event_pex_rst_deassert()\")\nReviewed-by: Jon Hunter \nTested-by: Jon Hunter \nReviewed-by: Vidya Sagar \nSigned-off-by: Manikanta Maddireddy \n---\nChanges V1 -> V8: None\n\n drivers/pci/controller/dwc/pcie-tegra194.c | 8 ++++----\n 1 file changed, 4 insertions(+), 4 deletions(-)","diff":"diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c\nindex c7cae3a004ec..b497b178bb7e 100644\n--- a/drivers/pci/controller/dwc/pcie-tegra194.c\n+++ b/drivers/pci/controller/dwc/pcie-tegra194.c\n@@ -1749,10 +1749,6 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)\n \t\tgoto fail_phy;\n \t}\n \n-\t/* Perform cleanup that requires refclk */\n-\tpci_epc_deinit_notify(pcie->pci.ep.epc);\n-\tdw_pcie_ep_cleanup(&pcie->pci.ep);\n-\n \t/* Clear any stale interrupt statuses */\n \tappl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0);\n \tappl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0);\n@@ -1822,6 +1818,10 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)\n \n \treset_control_deassert(pcie->core_rst);\n \n+\t/* Perform cleanup that requires refclk and core reset deasserted */\n+\tpci_epc_deinit_notify(pcie->pci.ep.epc);\n+\tdw_pcie_ep_cleanup(&pcie->pci.ep);\n+\n \tval = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);\n \tval &= ~PORT_LOGIC_SPEED_CHANGE;\n \tdw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);\n","prefixes":["v8","14/14"]}