{"id":2215550,"url":"http://patchwork.ozlabs.org/api/patches/2215550/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260324190755.1094879-13-mmaddireddy@nvidia.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260324190755.1094879-13-mmaddireddy@nvidia.com>","list_archive_url":null,"date":"2026-03-24T19:07:53","name":"[v8,12/14] PCI: dwc: Apply ECRC workaround to DesignWare 5.00a as well","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"0e433bfa6a1fd1829066e1b4ee9865d5a45b7091","submitter":{"id":72399,"url":"http://patchwork.ozlabs.org/api/people/72399/?format=json","name":"Manikanta Maddireddy","email":"mmaddireddy@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260324190755.1094879-13-mmaddireddy@nvidia.com/mbox/","series":[{"id":497331,"url":"http://patchwork.ozlabs.org/api/series/497331/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=497331","date":"2026-03-24T19:07:42","name":"Fixes to pcie-tegra194 driver","version":8,"mbox":"http://patchwork.ozlabs.org/series/497331/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2215550/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2215550/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=SS07fZWd;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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Tegra234 SoC has 5.00a DWC HW version, which has\nthe same ATU TD override behaviour, so apply the workaround for 5.00a\ntoo.\n\nFixes: a54e19073718 (\"PCI: tegra194: Add Tegra234 PCIe support\")\nReviewed-by: Jon Hunter \nTested-by: Jon Hunter \nReviewed-by: Vidya Sagar \nSigned-off-by: Manikanta Maddireddy \n---\nChanges V8: Split into two patches\nChanges V1 -> V7: None\n\n drivers/pci/controller/dwc/pcie-designware.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)","diff":"diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c\nindex 345365ea97c7..c4dc2d88649e 100644\n--- a/drivers/pci/controller/dwc/pcie-designware.c\n+++ b/drivers/pci/controller/dwc/pcie-designware.c\n@@ -486,7 +486,7 @@ static inline void dw_pcie_writel_atu_ob(struct dw_pcie *pci, u32 index, u32 reg\n static inline u32 dw_pcie_enable_ecrc(u32 val)\n {\n \t/*\n-\t * DesignWare core version 4.90A has a design issue where the 'TD'\n+\t * DWC versions 0x3530302a and 0x3536322a has a design issue where the 'TD'\n \t * bit in the Control register-1 of the ATU outbound region acts\n \t * like an override for the ECRC setting, i.e., the presence of TLP\n \t * Digest (ECRC) in the outgoing TLPs is solely determined by this\n@@ -559,7 +559,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,\n \tif (upper_32_bits(limit_addr) > upper_32_bits(parent_bus_addr) &&\n \t dw_pcie_ver_is_ge(pci, 460A))\n \t\tval |= PCIE_ATU_INCREASE_REGION_SIZE;\n-\tif (dw_pcie_ver_is(pci, 490A))\n+\tif (dw_pcie_ver_is(pci, 490A) || dw_pcie_ver_is(pci, 500A))\n \t\tval = dw_pcie_enable_ecrc(val);\n \tdw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);\n \n","prefixes":["v8","12/14"]}