{"id":2215546,"url":"http://patchwork.ozlabs.org/api/patches/2215546/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260324190755.1094879-5-mmaddireddy@nvidia.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260324190755.1094879-5-mmaddireddy@nvidia.com>","list_archive_url":null,"date":"2026-03-24T19:07:45","name":"[v8,04/14] PCI: tegra194: Don't force the device into the D0 state before L2","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"7fe5107bf3a9949c79aa93e109609d617ac1c514","submitter":{"id":72399,"url":"http://patchwork.ozlabs.org/api/people/72399/?format=json","name":"Manikanta Maddireddy","email":"mmaddireddy@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260324190755.1094879-5-mmaddireddy@nvidia.com/mbox/","series":[{"id":497331,"url":"http://patchwork.ozlabs.org/api/series/497331/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=497331","date":"2026-03-24T19:07:42","name":"Fixes to pcie-tegra194 driver","version":8,"mbox":"http://patchwork.ozlabs.org/series/497331/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2215546/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2215546/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=phHDiWto;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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The previous workaround that\nforced downstream devices to D0 before taking the link to L2 cited PCI\nExpress Base r4.0 v1.0 sec 5.2 Link State Power Management; however, that\nspec does not explicitly require putting the device into D0 and only\nindicates that power removal may be initiated without transitioning to\nD3Hot.\n\nRemove the D0 workaround so that Endpoint devices can use wake\nfunctionality (WAKE# from D3). With some Endpoints the link may not enter\nL2 when they remain in D3, but the Root Port continues with the usual\nflow after PME timeout, so there is no functional issue.\n\nFixes: 56e15a238d92 (\"PCI: tegra: Add Tegra194 PCIe support\")\nReviewed-by: Jon Hunter \nTested-by: Jon Hunter \nSigned-off-by: Vidya Sagar \nSigned-off-by: Manikanta Maddireddy \n---\nChanges V6 -> V8: Fix commit message\nChanges V1 -> V6: None\n\n drivers/pci/controller/dwc/pcie-tegra194.c | 41 ----------------------\n 1 file changed, 41 deletions(-)","diff":"diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c\nindex baee73438638..7e15597df6c1 100644\n--- a/drivers/pci/controller/dwc/pcie-tegra194.c\n+++ b/drivers/pci/controller/dwc/pcie-tegra194.c\n@@ -1258,44 +1258,6 @@ static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie,\n \treturn 0;\n }\n \n-static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie)\n-{\n-\tstruct dw_pcie_rp *pp = &pcie->pci.pp;\n-\tstruct pci_bus *child, *root_port_bus = NULL;\n-\tstruct pci_dev *pdev;\n-\n-\t/*\n-\t * link doesn't go into L2 state with some of the endpoints with Tegra\n-\t * if they are not in D0 state. So, need to make sure that immediate\n-\t * downstream devices are in D0 state before sending PME_TurnOff to put\n-\t * link into L2 state.\n-\t * This is as per PCI Express Base r4.0 v1.0 September 27-2017,\n-\t * 5.2 Link State Power Management (Page #428).\n-\t */\n-\n-\tlist_for_each_entry(child, &pp->bridge->bus->children, node) {\n-\t\tif (child->parent == pp->bridge->bus) {\n-\t\t\troot_port_bus = child;\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-\n-\tif (!root_port_bus) {\n-\t\tdev_err(pcie->dev, \"Failed to find downstream bus of Root Port\\n\");\n-\t\treturn;\n-\t}\n-\n-\t/* Bring downstream devices to D0 if they are not already in */\n-\tlist_for_each_entry(pdev, &root_port_bus->devices, bus_list) {\n-\t\tif (PCI_SLOT(pdev->devfn) == 0) {\n-\t\t\tif (pci_set_power_state(pdev, PCI_D0))\n-\t\t\t\tdev_err(pcie->dev,\n-\t\t\t\t\t\"Failed to transition %s to D0 state\\n\",\n-\t\t\t\t\tdev_name(&pdev->dev));\n-\t\t}\n-\t}\n-}\n-\n static int tegra_pcie_get_slot_regulators(struct tegra_pcie_dw *pcie)\n {\n \tpcie->slot_ctl_3v3 = devm_regulator_get_optional(pcie->dev, \"vpcie3v3\");\n@@ -1625,7 +1587,6 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)\n \n static void tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie)\n {\n-\ttegra_pcie_downstream_dev_to_D0(pcie);\n \tdw_pcie_host_deinit(&pcie->pci.pp);\n \ttegra_pcie_dw_pme_turnoff(pcie);\n \ttegra_pcie_unconfig_controller(pcie);\n@@ -2335,7 +2296,6 @@ static int tegra_pcie_dw_suspend_noirq(struct device *dev)\n \tif (!pcie->link_state)\n \t\treturn 0;\n \n-\ttegra_pcie_downstream_dev_to_D0(pcie);\n \ttegra_pcie_dw_pme_turnoff(pcie);\n \ttegra_pcie_unconfig_controller(pcie);\n \n@@ -2409,7 +2369,6 @@ static void tegra_pcie_dw_shutdown(struct platform_device *pdev)\n \t\t\treturn;\n \n \t\tdebugfs_remove_recursive(pcie->debugfs);\n-\t\ttegra_pcie_downstream_dev_to_D0(pcie);\n \n \t\tdisable_irq(pcie->pci.pp.irq);\n \t\tif (IS_ENABLED(CONFIG_PCI_MSI))\n","prefixes":["v8","04/14"]}