{"id":2215543,"url":"http://patchwork.ozlabs.org/api/patches/2215543/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260324191000.1095768-10-mmaddireddy@nvidia.com/","project":{"id":21,"url":"http://patchwork.ozlabs.org/api/projects/21/?format=json","name":"Linux Tegra Development","link_name":"linux-tegra","list_id":"linux-tegra.vger.kernel.org","list_email":"linux-tegra@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260324191000.1095768-10-mmaddireddy@nvidia.com>","list_archive_url":null,"date":"2026-03-24T19:10:00","name":"[v8,9/9] PCI: tegra194: Use aspm-l1-entry-delay-ns DT property for L1 entrance latency","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"d930f10a12f568dd3b681bab4eb95149ac971c41","submitter":{"id":72399,"url":"http://patchwork.ozlabs.org/api/people/72399/?format=json","name":"Manikanta Maddireddy","email":"mmaddireddy@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260324191000.1095768-10-mmaddireddy@nvidia.com/mbox/","series":[{"id":497332,"url":"http://patchwork.ozlabs.org/api/series/497332/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/list/?series=497332","date":"2026-03-24T19:09:52","name":"Enhancements to pcie-tegra194 driver","version":8,"mbox":"http://patchwork.ozlabs.org/series/497332/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2215543/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2215543/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=C/DHt1oA;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; 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Convert the value from nanoseconds\nto the hardware encoding (log2(us) + 1, 3-bit field). If the property is\nabsent, default to 7 (maximum latency).\n\nSigned-off-by: Manikanta Maddireddy \n---\nChanges V8: Use aspm-l1-entry-delay-ns instead of of_data\nChanges V1 -> V7: None\n\n drivers/pci/controller/dwc/pcie-tegra194.c | 14 ++++++++++++++\n 1 file changed, 14 insertions(+)","diff":"diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c\nindex 3278353b2c29..a856a48362df 100644\n--- a/drivers/pci/controller/dwc/pcie-tegra194.c\n+++ b/drivers/pci/controller/dwc/pcie-tegra194.c\n@@ -18,6 +18,7 @@\n #include \n #include \n #include \n+#include \n #include \n #include \n #include \n@@ -272,6 +273,7 @@ struct tegra_pcie_dw {\n \tu32 aspm_cmrt;\n \tu32 aspm_pwr_on_t;\n \tu32 aspm_l0s_enter_lat;\n+\tu32 aspm_l1_enter_lat;\n \n \tstruct regulator *pex_ctl_supply;\n \tstruct regulator *slot_ctl_3v3;\n@@ -710,6 +712,8 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie)\n \tval = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);\n \tval &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK;\n \tval |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT);\n+\tval &= ~PORT_AFR_L1_ENTRANCE_LAT_MASK;\n+\tval |= (pcie->aspm_l1_enter_lat << PORT_AFR_L1_ENTRANCE_LAT_SHIFT);\n \tval |= PORT_AFR_ENTER_ASPM;\n \tdw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);\n }\n@@ -1110,6 +1114,7 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)\n {\n \tstruct platform_device *pdev = to_platform_device(pcie->dev);\n \tstruct device_node *np = pcie->dev->of_node;\n+\tu32 val;\n \tint ret;\n \n \tpcie->dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"dbi\");\n@@ -1136,6 +1141,15 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)\n \t\tdev_info(pcie->dev,\n \t\t\t \"Failed to read ASPM L0s Entrance latency: %d\\n\", ret);\n \n+\t/* Default to max latency of 7. */\n+\tpcie->aspm_l1_enter_lat = 7;\n+\tret = of_property_read_u32(np, \"aspm-l1-entry-delay-ns\", &val);\n+\tif (!ret) {\n+\t\tu32 us = max(val / 1000, 1U);\n+\n+\t\tpcie->aspm_l1_enter_lat = min(ilog2(us) + 1, 7U);\n+\t}\n+\n \tret = of_property_read_u32(np, \"num-lanes\", &pcie->num_lanes);\n \tif (ret < 0) {\n \t\tdev_err(pcie->dev, \"Failed to read num-lanes: %d\\n\", ret);\n","prefixes":["v8","9/9"]}