{"id":2215538,"url":"http://patchwork.ozlabs.org/api/patches/2215538/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260324190755.1094879-9-mmaddireddy@nvidia.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260324190755.1094879-9-mmaddireddy@nvidia.com>","list_archive_url":null,"date":"2026-03-24T19:07:49","name":"[v8,08/14] PCI: tegra194: Set LTR message request before PCIe link up","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"cada2e2dc8650d2cb368a77d8a21e8015be3d5bf","submitter":{"id":72399,"url":"http://patchwork.ozlabs.org/api/people/72399/?format=json","name":"Manikanta Maddireddy","email":"mmaddireddy@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260324190755.1094879-9-mmaddireddy@nvidia.com/mbox/","series":[{"id":497331,"url":"http://patchwork.ozlabs.org/api/series/497331/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=497331","date":"2026-03-24T19:07:42","name":"Fixes to pcie-tegra194 driver","version":8,"mbox":"http://patchwork.ozlabs.org/series/497331/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2215538/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2215538/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=lA9mf+XR;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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Set snoop and no-snoop LTR timing and LTR message request before\nthe PCIe link comes up so that the LTR message is sent upstream as soon as\nLTR is enabled.\n\nThis addresses the case where the host has not yet programmed Max Snoop/\nNo-Snoop latencies in config space. Without programming these values, the\nEndpoint would send 0 latencies to the host. The hardware later compares\nthese requested values with the Max latencies configured by the host and\nsends the appropriate values upstream once the host sets them.\n\nFixes: c57247f940e8 (\"PCI: tegra: Add support for PCIe endpoint mode in Tegra194\")\nReviewed-by: Jon Hunter \nTested-by: Jon Hunter \nSigned-off-by: Vidya Sagar \nSigned-off-by: Manikanta Maddireddy \n---\nChanges V8: Fix commit message\nChanges V6 -> V7: Retain FIELD_PREP() usage\nChanges V1 -> V6: None\n\n drivers/pci/controller/dwc/pcie-tegra194.c | 18 +++++++++---------\n 1 file changed, 9 insertions(+), 9 deletions(-)","diff":"diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c\nindex 0be701e58238..602ff8131887 100644\n--- a/drivers/pci/controller/dwc/pcie-tegra194.c\n+++ b/drivers/pci/controller/dwc/pcie-tegra194.c\n@@ -485,15 +485,6 @@ static irqreturn_t tegra_pcie_ep_irq_thread(int irq, void *arg)\n \tif (val & PCI_COMMAND_MASTER) {\n \t\tktime_t timeout;\n \n-\t\t/* 110us for both snoop and no-snoop */\n-\t\tval = FIELD_PREP(PCI_LTR_VALUE_MASK, 110) |\n-\t\t FIELD_PREP(PCI_LTR_SCALE_MASK, 2) |\n-\t\t LTR_MSG_REQ |\n-\t\t FIELD_PREP(PCI_LTR_NOSNOOP_VALUE, 110) |\n-\t\t FIELD_PREP(PCI_LTR_NOSNOOP_SCALE, 2) |\n-\t\t LTR_NOSNOOP_MSG_REQ;\n-\t\tappl_writel(pcie, val, APPL_LTR_MSG_1);\n-\n \t\t/* Send LTR upstream */\n \t\tval = appl_readl(pcie, APPL_LTR_MSG_2);\n \t\tval |= APPL_LTR_MSG_2_LTR_MSG_REQ_STATE;\n@@ -1803,6 +1794,15 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)\n \tval |= APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN;\n \tappl_writel(pcie, val, APPL_INTR_EN_L1_0_0);\n \n+\t/* 110us for both snoop and no-snoop */\n+\tval = FIELD_PREP(PCI_LTR_VALUE_MASK, 110) |\n+\t FIELD_PREP(PCI_LTR_SCALE_MASK, 2) |\n+\t LTR_MSG_REQ |\n+\t FIELD_PREP(PCI_LTR_NOSNOOP_VALUE, 110) |\n+\t FIELD_PREP(PCI_LTR_NOSNOOP_SCALE, 2) |\n+\t LTR_NOSNOOP_MSG_REQ;\n+\tappl_writel(pcie, val, APPL_LTR_MSG_1);\n+\n \treset_control_deassert(pcie->core_rst);\n \n \tval = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);\n","prefixes":["v8","08/14"]}