{"id":2215525,"url":"http://patchwork.ozlabs.org/api/patches/2215525/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260324190755.1094879-3-mmaddireddy@nvidia.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260324190755.1094879-3-mmaddireddy@nvidia.com>","list_archive_url":null,"date":"2026-03-24T19:07:43","name":"[v8,02/14] PCI: tegra194: Increase LTSSM poll time on surprise down","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"e7496181d2f1e83f7d10bedc403479d89e513617","submitter":{"id":72399,"url":"http://patchwork.ozlabs.org/api/people/72399/?format=json","name":"Manikanta Maddireddy","email":"mmaddireddy@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260324190755.1094879-3-mmaddireddy@nvidia.com/mbox/","series":[{"id":497331,"url":"http://patchwork.ozlabs.org/api/series/497331/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=497331","date":"2026-03-24T19:07:42","name":"Fixes to pcie-tegra194 driver","version":8,"mbox":"http://patchwork.ozlabs.org/series/497331/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2215525/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2215525/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=f38mGZDq;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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Recovery.RcvrLock\nand Recovery.RcvrSpeed transit times are 24 ms and 48 ms respectively, so\nthe total time from L0 to detect is ~96 ms. Increase the poll timeout to\n120 ms to account for this.\n\nAdd LTSSM state defines for detect-related states and use them in the\npoll condition. Use readl_poll_timeout() instead of readl_poll_timeout_atomic()\nin tegra_pcie_dw_pme_turnoff() since that path runs in non-atomic context.\n\nFixes: 56e15a238d92 (\"PCI: tegra: Add Tegra194 PCIe support\")\nReviewed-by: Jon Hunter \nTested-by: Jon Hunter \nSigned-off-by: Vidya Sagar \nSigned-off-by: Manikanta Maddireddy \n---\nChanges V8: Split into two patches\nChanges V6 -> V7: Append _US to LTSSM macros\nChanges V5 -> V6: Retain only one fixes tag\nChanges V1 -> V5: None\n\n drivers/pci/controller/dwc/pcie-tegra194.c | 36 +++++++++++++---------\n 1 file changed, 21 insertions(+), 15 deletions(-)","diff":"diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c\nindex d6c6bd512b51..5b243c006562 100644\n--- a/drivers/pci/controller/dwc/pcie-tegra194.c\n+++ b/drivers/pci/controller/dwc/pcie-tegra194.c\n@@ -137,7 +137,11 @@\n #define APPL_DEBUG_PM_LINKST_IN_L0\t\t0x11\n #define APPL_DEBUG_LTSSM_STATE_MASK\t\tGENMASK(8, 3)\n #define APPL_DEBUG_LTSSM_STATE_SHIFT\t\t3\n-#define LTSSM_STATE_PRE_DETECT\t\t\t5\n+#define LTSSM_STATE_DETECT_QUIET\t\t0x00\n+#define LTSSM_STATE_DETECT_ACT\t\t\t0x08\n+#define LTSSM_STATE_PRE_DETECT_QUIET\t\t0x28\n+#define LTSSM_STATE_DETECT_WAIT\t\t\t0x30\n+#define LTSSM_STATE_L2_IDLE\t\t\t0xa8\n \n #define APPL_RADM_STATUS\t\t\t0xE4\n #define APPL_PM_XMT_TURNOFF_STATE\t\tBIT(0)\n@@ -198,7 +202,8 @@\n #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK\tGENMASK(11, 8)\n #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT\t8\n \n-#define LTSSM_TIMEOUT 50000\t/* 50ms */\n+#define LTSSM_DELAY_US\t\t10000\t/* 10 ms */\n+#define LTSSM_TIMEOUT_US\t120000\t/* 120 ms */\n \n #define GEN3_GEN4_EQ_PRESET_INIT\t5\n \n@@ -1597,15 +1602,14 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)\n \t\tdata &= ~APPL_CTRL_LTSSM_EN;\n \t\twritel(data, pcie->appl_base + APPL_CTRL);\n \n-\t\terr = readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG,\n-\t\t\t\t\t\tdata,\n-\t\t\t\t\t\t((data &\n-\t\t\t\t\t\tAPPL_DEBUG_LTSSM_STATE_MASK) >>\n-\t\t\t\t\t\tAPPL_DEBUG_LTSSM_STATE_SHIFT) ==\n-\t\t\t\t\t\tLTSSM_STATE_PRE_DETECT,\n-\t\t\t\t\t\t1, LTSSM_TIMEOUT);\n+\t\terr = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, data,\n+\t\t\t((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_QUIET) ||\n+\t\t\t((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_ACT) ||\n+\t\t\t((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_PRE_DETECT_QUIET) ||\n+\t\t\t((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_WAIT),\n+\t\t\tLTSSM_DELAY_US, LTSSM_TIMEOUT_US);\n \t\tif (err)\n-\t\t\tdev_info(pcie->dev, \"Link didn't go to detect state\\n\");\n+\t\t\tdev_info(pcie->dev, \"LTSSM state: 0x%x detect timeout: %d\\n\", data, err);\n \t}\n \t/*\n \t * DBI registers may not be accessible after this as PLL-E would be\n@@ -1685,12 +1689,14 @@ static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie)\n \tappl_writel(pcie, val, APPL_CTRL);\n \n \tret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val,\n-\t\t\t\t ((val & APPL_DEBUG_LTSSM_STATE_MASK) >>\n-\t\t\t\t APPL_DEBUG_LTSSM_STATE_SHIFT) ==\n-\t\t\t\t LTSSM_STATE_PRE_DETECT,\n-\t\t\t\t 1, LTSSM_TIMEOUT);\n+\t\t((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_QUIET) ||\n+\t\t((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_ACT) ||\n+\t\t((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_PRE_DETECT_QUIET) ||\n+\t\t((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_WAIT) ||\n+\t\t((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_L2_IDLE),\n+\t\tLTSSM_DELAY_US, LTSSM_TIMEOUT_US);\n \tif (ret)\n-\t\tdev_err(pcie->dev, \"Failed to go Detect state: %d\\n\", ret);\n+\t\tdev_info(pcie->dev, \"LTSSM state: 0x%x detect timeout: %d\\n\", val, ret);\n \n \treset_control_assert(pcie->core_rst);\n \n","prefixes":["v8","02/14"]}