{"id":2215521,"url":"http://patchwork.ozlabs.org/api/patches/2215521/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260324190755.1094879-2-mmaddireddy@nvidia.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260324190755.1094879-2-mmaddireddy@nvidia.com>","list_archive_url":null,"date":"2026-03-24T19:07:42","name":"[v8,01/14] PCI: tegra194: Fix polling delay for L2 state","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"ffc2e0ccfeb1bae9b3afa2613fcdacfe44bf6b4b","submitter":{"id":72399,"url":"http://patchwork.ozlabs.org/api/people/72399/?format=json","name":"Manikanta Maddireddy","email":"mmaddireddy@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260324190755.1094879-2-mmaddireddy@nvidia.com/mbox/","series":[{"id":497331,"url":"http://patchwork.ozlabs.org/api/series/497331/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=497331","date":"2026-03-24T19:07:42","name":"Fixes to pcie-tegra194 driver","version":8,"mbox":"http://patchwork.ozlabs.org/series/497331/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2215521/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2215521/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=DeW+VwBg;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; 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Currently,\ndriver is polling for 10 msec with 1 usec delay which is aggressive.\nUse existing macro PCIE_PME_TO_L2_TIMEOUT_US to poll for 10 msec with\n1 msec delay. Since this function is used in non-atomic context only,\nuse non-atomic poll function.\n\nFixes: 56e15a238d92 (\"PCI: tegra: Add Tegra194 PCIe support\")\nReviewed-by: Jon Hunter \nTested-by: Jon Hunter \nSigned-off-by: Vidya Sagar \nSigned-off-by: Manikanta Maddireddy \n---\nChanges V8: None\nChanges V6 -> V7: Use PCIE_PME_TO_L2_TIMEOUT_US instead PME_ACK_TIMEOUT\nChanges V1 -> V6: None\n\n drivers/pci/controller/dwc/pcie-tegra194.c | 9 ++++-----\n 1 file changed, 4 insertions(+), 5 deletions(-)","diff":"diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c\nindex 0ddeef70726d..d6c6bd512b51 100644\n--- a/drivers/pci/controller/dwc/pcie-tegra194.c\n+++ b/drivers/pci/controller/dwc/pcie-tegra194.c\n@@ -198,8 +198,6 @@\n #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK\tGENMASK(11, 8)\n #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT\t8\n \n-#define PME_ACK_TIMEOUT 10000\n-\n #define LTSSM_TIMEOUT 50000\t/* 50ms */\n \n #define GEN3_GEN4_EQ_PRESET_INIT\t5\n@@ -1553,9 +1551,10 @@ static int tegra_pcie_try_link_l2(struct tegra_pcie_dw *pcie)\n \tval |= APPL_PM_XMT_TURNOFF_STATE;\n \tappl_writel(pcie, val, APPL_RADM_STATUS);\n \n-\treturn readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, val,\n-\t\t\t\t val & APPL_DEBUG_PM_LINKST_IN_L2_LAT,\n-\t\t\t\t 1, PME_ACK_TIMEOUT);\n+\treturn readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val,\n+\t\t\t\t val & APPL_DEBUG_PM_LINKST_IN_L2_LAT,\n+\t\t\t\t PCIE_PME_TO_L2_TIMEOUT_US/10,\n+\t\t\t\t PCIE_PME_TO_L2_TIMEOUT_US);\n }\n \n static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)\n","prefixes":["v8","01/14"]}