{"id":2215450,"url":"http://patchwork.ozlabs.org/api/patches/2215450/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260324164007.549397-6-djordje.todorovic@htecgroup.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260324164007.549397-6-djordje.todorovic@htecgroup.com>","list_archive_url":null,"date":"2026-03-24T16:40:16","name":"[v5,5/7] target/riscv: Fix page table walk endianness for big-endian harts","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"6bf9d371901936c1761fae33dd4ac76c90d33921","submitter":{"id":90738,"url":"http://patchwork.ozlabs.org/api/people/90738/?format=json","name":"Djordje Todorovic","email":"Djordje.Todorovic@htecgroup.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260324164007.549397-6-djordje.todorovic@htecgroup.com/mbox/","series":[{"id":497314,"url":"http://patchwork.ozlabs.org/api/series/497314/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497314","date":"2026-03-24T16:40:16","name":"Add RISC-V big-endian target support","version":5,"mbox":"http://patchwork.ozlabs.org/series/497314/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2215450/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2215450/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=htecgroup.com header.i=@htecgroup.com\n header.a=rsa-sha256 header.s=selector1 header.b=f8t9cZ8r;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"utf-8\"","Content-ID":"","Content-Transfer-Encoding":"base64","MIME-Version":"1.0","X-OriginatorOrg":"htecgroup.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-AuthSource":"GV2PR09MB8755.eurprd09.prod.outlook.com","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 4952dbfb-f2c3-4459-cee8-08de89c407fb","X-MS-Exchange-CrossTenant-originalarrivaltime":"24 Mar 2026 16:40:16.7726 (UTC)","X-MS-Exchange-CrossTenant-fromentityheader":"Hosted","X-MS-Exchange-CrossTenant-id":"9f85665b-7efd-4776-9dfe-b6bfda2565ee","X-MS-Exchange-CrossTenant-mailboxtype":"HOSTED","X-MS-Exchange-CrossTenant-userprincipalname":"\n ECF3ls8deg3gWNX4zoXFRw7uZDlxYxATcBI1Md2KcFAtLui0reVq3ktsDRjwvFJA8aj6wNjODKC4n6ZbKuj6byDOXNdLaBV1JSO54tTaOdM=","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"VI0PR09MB7005","Received-SPF":"pass client-ip=2a01:111:f403:c201::3;\n envelope-from=Djordje.Todorovic@htecgroup.com;\n helo=AS8PR04CU009.outbound.protection.outlook.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"The page table walker reads PTEs using address_space_ldl/ldq which use\ncompile-time native endianness (always LE for RISC-V). However, when a\nbig-endian kernel writes PTEs via normal store instructions, they are\nstored in big-endian byte order. The walker then misinterprets the PTE\nvalues, causing page faults and a hang when the kernel enables the MMU.\n\nThe RISC-V privileged specification states that implicit data memory\naccesses to supervisor-level memory management data structures follow\nthe hart's endianness setting (MSTATUS SBE/MBE bits).\n\nFix both PTE reads and atomic A/D bit updates to use the explicit _le\nor _be memory access variants based on the hart's runtime endianness.\n\nSigned-off-by: Djordje Todorovic \nReviewed-by: Philippe Mathieu-Daudé \n---\n target/riscv/cpu_helper.c | 28 ++++++++++++++++++++++------\n 1 file changed, 22 insertions(+), 6 deletions(-)","diff":"diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c\r\nindex c28832e0e3..b3d33da13e 100644\r\n--- a/target/riscv/cpu_helper.c\r\n+++ b/target/riscv/cpu_helper.c\r\n@@ -1365,9 +1365,13 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,\r\n }\r\n \r\n if (riscv_cpu_mxl(env) == MXL_RV32) {\r\n- pte = address_space_ldl_le(cs->as, pte_addr, attrs, &res);\r\n+ pte = riscv_cpu_data_is_big_endian(env)\r\n+ ? address_space_ldl_be(cs->as, pte_addr, attrs, &res)\r\n+ : address_space_ldl_le(cs->as, pte_addr, attrs, &res);\r\n } else {\r\n- pte = address_space_ldq_le(cs->as, pte_addr, attrs, &res);\r\n+ pte = riscv_cpu_data_is_big_endian(env)\r\n+ ? address_space_ldq_be(cs->as, pte_addr, attrs, &res)\r\n+ : address_space_ldq_le(cs->as, pte_addr, attrs, &res);\r\n }\r\n \r\n if (res != MEMTX_OK) {\r\n@@ -1566,12 +1570,24 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,\r\n if (memory_region_is_ram(mr)) {\r\n target_ulong *pte_pa = qemu_map_ram_ptr(mr->ram_block, addr1);\r\n target_ulong old_pte;\r\n+ bool be = riscv_cpu_data_is_big_endian(env);\r\n if (riscv_cpu_sxl(env) == MXL_RV32) {\r\n- old_pte = qatomic_cmpxchg((uint32_t *)pte_pa, cpu_to_le32(pte), cpu_to_le32(updated_pte));\r\n- old_pte = le32_to_cpu(old_pte);\r\n+ uint32_t cmp = be ? cpu_to_be32(pte)\r\n+ : cpu_to_le32(pte);\r\n+ uint32_t val = be ? cpu_to_be32(updated_pte)\r\n+ : cpu_to_le32(updated_pte);\r\n+ old_pte = qatomic_cmpxchg((uint32_t *)pte_pa,\r\n+ cmp, val);\r\n+ old_pte = be ? be32_to_cpu(old_pte)\r\n+ : le32_to_cpu(old_pte);\r\n } else {\r\n- old_pte = qatomic_cmpxchg(pte_pa, cpu_to_le64(pte), cpu_to_le64(updated_pte));\r\n- old_pte = le64_to_cpu(old_pte);\r\n+ target_ulong cmp = be ? cpu_to_be64(pte)\r\n+ : cpu_to_le64(pte);\r\n+ target_ulong val = be ? cpu_to_be64(updated_pte)\r\n+ : cpu_to_le64(updated_pte);\r\n+ old_pte = qatomic_cmpxchg(pte_pa, cmp, val);\r\n+ old_pte = be ? be64_to_cpu(old_pte)\r\n+ : le64_to_cpu(old_pte);\r\n }\r\n if (old_pte != pte) {\r\n goto restart;\r\n","prefixes":["v5","5/7"]}